Archives are refreshed every 30 minutes - for details, please visit
the main index
.
You can also
download the archives in mbox format
.
qemu-riscv (thread)
[
Date Index
][
Top
][
All Lists
]
Advanced
[
Prev Period
]
Last Modified: Sun Mar 31 2019 23:12:36 -0400
Threads in reverse chronological order
[
Next Period
]
[Qemu-riscv] [PATCH for-4.1 0/8] target/riscv: decodetree improvments
,
Richard Henderson
,
2019/03/31
[Qemu-riscv] [PATCH for-4.1 1/8] target/riscv: Name the argument sets for all of insn32 formats
,
Richard Henderson
,
2019/03/31
[Qemu-riscv] [PATCH for-4.1 2/8] target/riscv: Use --static-decode for decodetree
,
Richard Henderson
,
2019/03/31
[Qemu-riscv] [PATCH for-4.1 4/8] target/riscv: Merge argument decode for RVC shifti
,
Richard Henderson
,
2019/03/31
[Qemu-riscv] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16
,
Richard Henderson
,
2019/03/31
[Qemu-riscv] [PATCH for-4.1 5/8] target/riscv: Use pattern groups in insn16.decode
,
Richard Henderson
,
2019/03/31
[Qemu-riscv] [PATCH for-4.1 6/8] target/riscv: Split RVC32 and RVC64 insns into separate files
,
Richard Henderson
,
2019/03/31
[Qemu-riscv] [PATCH for-4.1 7/8] target/riscv: Split gen_arith_imm into functional and temp
,
Richard Henderson
,
2019/03/31
[Qemu-riscv] [PATCH for-4.1 8/8] target/riscv: Remove spaces from register names
,
Richard Henderson
,
2019/03/31
[Qemu-riscv] [PATCH for 4.1 v2 0/6] RISC-V: Allow specifying CPU ISA via command line
,
Alistair Francis
,
2019/03/29
[Qemu-riscv] [PATCH for 4.1 v2 3/6] target/riscv: Create settable CPU properties
,
Alistair Francis
,
2019/03/29
[Qemu-riscv] [PATCH for 4.1 v2 1/6] linux-user/riscv: Add the CPU type as a comment
,
Alistair Francis
,
2019/03/29
[Qemu-riscv] [PATCH for 4.1 v2 5/6] target/riscv: Remove the generic no MMU CPUs
,
Alistair Francis
,
2019/03/29
[Qemu-riscv] [PATCH for 4.1 v2 4/6] riscv: virt: Allow specifying a CPU via commandline
,
Alistair Francis
,
2019/03/29
[Qemu-riscv] [PATCH for 4.1 v2 6/6] riscv: Add a generic spike machine
,
Alistair Francis
,
2019/03/29
[Qemu-riscv] [PATCH for 4.1 v2 2/6] target/riscv: Fall back to generating a RISC-V CPU
,
Alistair Francis
,
2019/03/29
[Qemu-riscv] [PATCH for 4.0 v2 0/2] Update the QEMU PLIC addresses
,
Alistair Francis
,
2019/03/27
[Qemu-riscv] [PATCH for 4.0 v2 2/2] riscv: plic: Log guest errors
,
Alistair Francis
,
2019/03/27
Re: [Qemu-riscv] [PATCH for 4.0 v2 2/2] riscv: plic: Log guest errors
,
Alistair Francis
,
2019/03/27
Re: [Qemu-riscv] [PATCH for 4.0 v2 2/2] riscv: plic: Log guest errors
,
Palmer Dabbelt
,
2019/03/27
[Qemu-riscv] [PATCH for 4.0 v2 1/2] riscv: plic: Fix incorrect irq calculation
,
Alistair Francis
,
2019/03/27
Message not available
Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.0 v2 2/2] riscv: plic: Log guest errors
,
Philippe Mathieu-Daudé
,
2019/03/27
Re: [Qemu-riscv] [PATCH for 4.0 v2 0/2] Update the QEMU PLIC addresses
,
Palmer Dabbelt
,
2019/03/27
[Qemu-riscv] [PATCH] target/riscv: Fix wrong expanding for c.fswsp
,
Kito Cheng
,
2019/03/26
Re: [Qemu-riscv] [Qemu-devel] [PATCH] target/riscv: Fix wrong expanding for c.fswsp
,
no-reply
,
2019/03/27
[Qemu-riscv] [PULL] A second RISC-V Patch for 4.0.0-rc1
,
Palmer Dabbelt
,
2019/03/26
[Qemu-riscv] [PULL] target/riscv: Fix wrong expanding for c.fswsp
,
Palmer Dabbelt
,
2019/03/26
Re: [Qemu-riscv] [PULL] A second RISC-V Patch for 4.0.0-rc1
,
Peter Maydell
,
2019/03/26
Re: [Qemu-riscv] [PATCH] SiFive RISC-V GPIO Device
,
Palmer Dabbelt
,
2019/03/26
Re: [Qemu-riscv] [PATCH] SiFive RISC-V GPIO Device
,
Fabien Chouteau
,
2019/03/26
Re: [Qemu-riscv] [PATCH] SiFive RISC-V GPIO Device
,
Palmer Dabbelt
,
2019/03/26
[Qemu-riscv] [PULL] A Single RISC-V Patch for 4.0-rc1
,
Palmer Dabbelt
,
2019/03/26
[Qemu-riscv] [PULL] target/riscv: Zero extend the inputs of divuw and remuw
,
Palmer Dabbelt
,
2019/03/26
Re: [Qemu-riscv] [PULL] A Single RISC-V Patch for 4.0-rc1
,
Peter Maydell
,
2019/03/26
[Qemu-riscv] [PATCH V2] RISC-V: fix single stepping over ret and other branching instructions
,
Fabien Chouteau
,
2019/03/25
Re: [Qemu-riscv] [PATCH V2] RISC-V: fix single stepping over ret and other branching instructions
,
Richard Henderson
,
2019/03/25
Re: [Qemu-riscv] [Qemu-devel] [PATCH V2] RISC-V: fix single stepping over ret and other branching instructions
,
Alistair Francis
,
2019/03/26
[Qemu-riscv] [PATCH v2 for-4.0] hardfloat: fix float32/64 fused multiply-add
,
Emilio G. Cota
,
2019/03/22
Re: [Qemu-riscv] [PATCH v2 for-4.0] hardfloat: fix float32/64 fused multiply-add
,
Alex Bennée
,
2019/03/23
Re: [Qemu-riscv] [PATCH v2 for-4.0] hardfloat: fix float32/64 fused multiply-add
,
Richard Henderson
,
2019/03/23
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 for-4.0] hardfloat: fix float32/64 fused multiply-add
,
Palmer Dabbelt
,
2019/03/25
[Qemu-riscv] [PATCH] hardfloat: fix float32/64 fused multiply-add
,
Kito Cheng
,
2019/03/22
Re: [Qemu-riscv] [PATCH] hardfloat: fix float32/64 fused multiply-add
,
Emilio G. Cota
,
2019/03/22
[Qemu-riscv] [PATCH] RISC-V: fix single stepping over ret and other branching instructions
,
Fabien Chouteau
,
2019/03/22
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISC-V: fix single stepping over ret and other branching instructions
,
Richard Henderson
,
2019/03/22
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISC-V: fix single stepping over ret and other branching instructions
,
Fabien Chouteau
,
2019/03/25
[Qemu-riscv] [PATCH] sifive_prci: Read and write PRCI registers
,
Palmer Dabbelt
,
2019/03/21
Re: [Qemu-riscv] [Qemu-devel] [PATCH] sifive_prci: Read and write PRCI registers
,
no-reply
,
2019/03/21
[Qemu-riscv] [PATCH] target/riscv: Zero extend the inputs of divuw and remuw
,
Palmer Dabbelt
,
2019/03/21
Re: [Qemu-riscv] [PATCH] target/riscv: Zero extend the inputs of divuw and remuw
,
Kito Cheng
,
2019/03/21
Re: [Qemu-riscv] [Qemu-devel] [PATCH] target/riscv: Zero extend the inputs of divuw and remuw
,
Richard Henderson
,
2019/03/21
[Qemu-riscv] [PATCH for 4.0 v1 0/5] Update the QEMU PLIC addresses
,
Alistair Francis
,
2019/03/20
[Qemu-riscv] [PATCH for 4.0 v1 4/5] riscv: virt: Fix PLIC priority base offset
,
Alistair Francis
,
2019/03/20
[Qemu-riscv] [PATCH for 4.0 v1 3/5] riscv: sifive_e: Fix PLIC priority base offset
,
Alistair Francis
,
2019/03/20
[Qemu-riscv] [PATCH for 4.0 v1 5/5] riscv: plic: Log guest errors
,
Alistair Francis
,
2019/03/20
[Qemu-riscv] [PATCH for 4.0 v1 1/5] riscv: plic: Fix incorrect irq calculation
,
Alistair Francis
,
2019/03/20
Re: [Qemu-riscv] [PATCH for 4.0 v1 1/5] riscv: plic: Fix incorrect irq calculation
,
Palmer Dabbelt
,
2019/03/27
Re: [Qemu-riscv] [PATCH for 4.0 v1 1/5] riscv: plic: Fix incorrect irq calculation
,
Alistair Francis
,
2019/03/27
Re: [Qemu-riscv] [PATCH for 4.0 v1 1/5] riscv: plic: Fix incorrect irq calculation
,
Palmer Dabbelt
,
2019/03/27
Re: [Qemu-riscv] [PATCH for 4.0 v1 1/5] riscv: plic: Fix incorrect irq calculation
,
Alistair Francis
,
2019/03/28
Re: [Qemu-riscv] [PATCH for 4.0 v1 1/5] riscv: plic: Fix incorrect irq calculation
,
Palmer Dabbelt
,
2019/03/29
[Qemu-riscv] [PATCH for 4.0 v1 2/5] riscv: sifive_u: Fix PLIC priority base offset and numbering
,
Alistair Francis
,
2019/03/20
Re: [Qemu-riscv] [PATCH for 4.0 v1 0/5] Update the QEMU PLIC addresses
,
Alistair Francis
,
2019/03/26
Re: [Qemu-riscv] [PATCH for 4.0 v1 0/5] Update the QEMU PLIC addresses
,
Palmer Dabbelt
,
2019/03/27
Message not available
Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.0 v1 5/5] riscv: plic: Log guest errors
,
Philippe Mathieu-Daudé
,
2019/03/26
[Qemu-riscv] [PATCH for 4.1 v1 0/6] RISC-V: Allow specifying CPU ISA via command line
,
Alistair Francis
,
2019/03/19
[Qemu-riscv] [PATCH for 4.1 v1 5/6] target/riscv: Remove the generic no MMU CPUs
,
Alistair Francis
,
2019/03/19
[Qemu-riscv] [PATCH for 4.1 v1 1/6] target/riscv: Fall back to generating a RISC-V CPU
,
Alistair Francis
,
2019/03/19
[Qemu-riscv] [PATCH for 4.1 v1 3/6] riscv: virt: Allow specifying a CPU via commandline
,
Alistair Francis
,
2019/03/19
[Qemu-riscv] [PATCH for 4.1 v1 4/6] target/riscvL Remove the unused any CPU
,
Alistair Francis
,
2019/03/19
Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v1 4/6] target/riscvL Remove the unused any CPU
,
Peter Maydell
,
2019/03/19
Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v1 4/6] target/riscvL Remove the unused any CPU
,
Alistair Francis
,
2019/03/20
[Qemu-riscv] [PATCH for 4.1 v1 2/6] target/riscv: Create settable CPU properties
,
Alistair Francis
,
2019/03/19
[Qemu-riscv] [PATCH for 4.1 v1 6/6] riscv: Add a generic spike machine
,
Alistair Francis
,
2019/03/19
[Qemu-riscv] [PULL] RISC-V Patches for 4.0-rc0, Part 2
,
Palmer Dabbelt
,
2019/03/19
[Qemu-riscv] [PULL 06/19] riscv: pmp: Log pmp access errors as guest errors
,
Palmer Dabbelt
,
2019/03/19
[Qemu-riscv] [PULL 19/19] riscv: sifive_u: Correct UART0's IRQ in the device tree
,
Palmer Dabbelt
,
2019/03/19
[Qemu-riscv] [PULL 18/19] riscv: sifive_uart: Generate TX interrupt
,
Palmer Dabbelt
,
2019/03/19
[Qemu-riscv] [PULL 17/19] target/riscv: Remove unused struct
,
Palmer Dabbelt
,
2019/03/19
[Qemu-riscv] [PULL 16/19] riscv: sifive_u: Allow up to 4 CPUs to be created
,
Palmer Dabbelt
,
2019/03/19
[Qemu-riscv] [PULL 15/19] RISC-V: Update load reservation comment in do_interrupt
,
Palmer Dabbelt
,
2019/03/19
[Qemu-riscv] [PULL 14/19] RISC-V: Convert trap debugging to trace events
,
Palmer Dabbelt
,
2019/03/19
[Qemu-riscv] [PULL 13/19] RISC-V: Add support for vectored interrupts
,
Palmer Dabbelt
,
2019/03/19
[Qemu-riscv] [PULL 12/19] RISC-V: Change local interrupts from edge to level
,
Palmer Dabbelt
,
2019/03/19
[Qemu-riscv] [PULL 11/19] RISC-V: linux-user support for RVE ABI
,
Palmer Dabbelt
,
2019/03/19
[Qemu-riscv] [PULL 10/19] elf: Add RISC-V PSABI ELF header defines
,
Palmer Dabbelt
,
2019/03/19
[Qemu-riscv] [PULL 09/19] RISC-V: Remove unnecessary disassembler constraints
,
Palmer Dabbelt
,
2019/03/19
[Qemu-riscv] [PULL 05/19] RISC-V: Add hooks to use the gdb xml files.
,
Palmer Dabbelt
,
2019/03/19
[Qemu-riscv] [PULL 07/19] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC
,
Palmer Dabbelt
,
2019/03/19
[Qemu-riscv] [PULL 08/19] RISC-V: Allow interrupt controllers to claim interrupts
,
Palmer Dabbelt
,
2019/03/19
[Qemu-riscv] [PULL 04/19] RISC-V: Add debug support for accessing CSRs.
,
Palmer Dabbelt
,
2019/03/19
[Qemu-riscv] [PULL 03/19] RISC-V: Fixes to CSR_* register macros.
,
Palmer Dabbelt
,
2019/03/19
[Qemu-riscv] [PULL 02/19] RISC-V: Add 64-bit gdb xml files.
,
Palmer Dabbelt
,
2019/03/19
[Qemu-riscv] [PULL 01/19] RISC-V: Add 32-bit gdb xml files.
,
Palmer Dabbelt
,
2019/03/19
Re: [Qemu-riscv] [PULL] RISC-V Patches for 4.0-rc0, Part 2
,
Peter Maydell
,
2019/03/19
Re: [Qemu-riscv] [PATCH] hw/riscv/virt: re-add machine-specific compatible string to /soc/ node
,
Palmer Dabbelt
,
2019/03/19
Re: [Qemu-riscv] [PATCH] hw/riscv/virt: re-add machine-specific compatible string to /soc/ node
,
Auer, Lukas
,
2019/03/19
[Qemu-riscv] [PULL] A Single RISC-V Patch for 4.0-rc0
,
Palmer Dabbelt
,
2019/03/18
[Qemu-riscv] [PULL] target/riscv: Fix manually parsed 16 bit insn
,
Palmer Dabbelt
,
2019/03/18
Re: [Qemu-riscv] [PULL] A Single RISC-V Patch for 4.0-rc0
,
Peter Maydell
,
2019/03/18
[Qemu-riscv] [PATCH 1/2] riscv: sifive_uart: Generate TX interrupt
,
Bin Meng
,
2019/03/17
[Qemu-riscv] [PATCH 2/2] riscv: sifive_u: Correct UART0's IRQ in the device tree
,
Bin Meng
,
2019/03/17
Re: [Qemu-riscv] [Qemu-devel] [PATCH 2/2] riscv: sifive_u: Correct UART0's IRQ in the device tree
,
Alistair Francis
,
2019/03/18
Re: [Qemu-riscv] [Qemu-devel] [PATCH 1/2] riscv: sifive_uart: Generate TX interrupt
,
Alistair Francis
,
2019/03/18
[Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4
,
Alistair Francis
,
2019/03/15
Re: [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4
,
Alistair Francis
,
2019/03/15
Re: [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4
,
Alistair Francis
,
2019/03/18
Re: [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4
,
Palmer Dabbelt
,
2019/03/18
Re: [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4
,
Alistair Francis
,
2019/03/19
[Qemu-riscv] [PATCH v1 11/12] riscv: sifive_u: Allow up to 4 CPUs to be created
,
Alistair Francis
,
2019/03/15
[Qemu-riscv] [PATCH v1 12/12] target/riscv: Remove unused struct
,
Alistair Francis
,
2019/03/15
[Qemu-riscv] [PATCH v1 10/12] RISC-V: Update load reservation comment in do_interrupt
,
Alistair Francis
,
2019/03/15
[Qemu-riscv] [PATCH v1 07/12] RISC-V: Change local interrupts from edge to level
,
Alistair Francis
,
2019/03/15
[Qemu-riscv] [PATCH v1 09/12] RISC-V: Convert trap debugging to trace events
,
Alistair Francis
,
2019/03/15
[Qemu-riscv] [PATCH v1 08/12] RISC-V: Add support for vectored interrupts
,
Alistair Francis
,
2019/03/15
[Qemu-riscv] [PATCH v1 06/12] RISC-V: linux-user support for RVE ABI
,
Alistair Francis
,
2019/03/15
[Qemu-riscv] [PATCH v1 05/12] elf: Add RISC-V PSABI ELF header defines
,
Alistair Francis
,
2019/03/15
[Qemu-riscv] [PATCH v1 03/12] RISC-V: Allow interrupt controllers to claim interrupts
,
Alistair Francis
,
2019/03/15
[Qemu-riscv] [PATCH v1 01/12] riscv: pmp: Log pmp access errors as guest errors
,
Alistair Francis
,
2019/03/15
[Qemu-riscv] [PATCH v1 04/12] RISC-V: Remove unnecessary disassembler constraints
,
Alistair Francis
,
2019/03/15
[Qemu-riscv] [PATCH v1 02/12] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC
,
Alistair Francis
,
2019/03/15
[Qemu-riscv] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true
,
Alistair Francis
,
2019/03/15
Re: [Qemu-riscv] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true
,
Paolo Bonzini
,
2019/03/18
Re: [Qemu-riscv] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true
,
Palmer Dabbelt
,
2019/03/18
Re: [Qemu-riscv] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true
,
Andrea Bolognani
,
2019/03/21
Re: [Qemu-riscv] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true
,
Paolo Bonzini
,
2019/03/21
Re: [Qemu-riscv] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true
,
Andrea Bolognani
,
2019/03/18
Re: [Qemu-riscv] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true
,
David Abdurachmanov
,
2019/03/18
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true
,
Markus Armbruster
,
2019/03/18
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true
,
Peter Maydell
,
2019/03/18
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true
,
Markus Armbruster
,
2019/03/18
Re: [Qemu-riscv] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true
,
Andrea Bolognani
,
2019/03/18
[Qemu-riscv] [PATCH] target/riscv: Fix manually parsed 16 bit insn
,
Bastian Koppelmann
,
2019/03/15
Re: [Qemu-riscv] [PATCH] target/riscv: Fix manually parsed 16 bit insn
,
Palmer Dabbelt
,
2019/03/15
Re: [Qemu-riscv] [Qemu-devel] [PATCH] target/riscv: Fix manually parsed 16 bit insn
,
Alistair Francis
,
2019/03/15
[Qemu-riscv] [PATCH v5 0/5] RISC-V: Add gdb xml files and gdbstub support
,
Chih-Min Chao
,
2019/03/15
[Qemu-riscv] [PATCH v5 3/5] RISC-V: Fixes to CSR_* register macros.
,
Chih-Min Chao
,
2019/03/15
[Qemu-riscv] [PATCH v5 1/5] RISC-V: Add 32-bit gdb xml files.
,
Chih-Min Chao
,
2019/03/15
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 1/5] RISC-V: Add 32-bit gdb xml files.
,
Alistair Francis
,
2019/03/15
[Qemu-riscv] [PATCH v5 5/5] RISC-V: Add hooks to use the gdb xml files.
,
Chih-Min Chao
,
2019/03/15
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 5/5] RISC-V: Add hooks to use the gdb xml files.
,
Alistair Francis
,
2019/03/15
[Qemu-riscv] [PATCH v5 2/5] RISC-V: Add 64-bit gdb xml files.
,
Chih-Min Chao
,
2019/03/15
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 2/5] RISC-V: Add 64-bit gdb xml files.
,
Alistair Francis
,
2019/03/15
[Qemu-riscv] [PATCH v5 4/5] RISC-V: Add debug support for accessing CSRs.
,
Chih-Min Chao
,
2019/03/15
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 0/5] RISC-V: Add gdb xml files and gdbstub support
,
Alistair Francis
,
2019/03/15
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 0/5] RISC-V: Add gdb xml files and gdbstub support
,
Palmer Dabbelt
,
2019/03/19
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 0/5] RISC-V: Add gdb xml files and gdbstub support
,
Peter Maydell
,
2019/03/19
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 0/5] RISC-V: Add gdb xml files and gdbstub support
,
Palmer Dabbelt
,
2019/03/19
Re: [Qemu-riscv] [Qemu-devel] [PULL 15/54] build: convert pci.mak to Kconfig
,
Andrea Bolognani
,
2019/03/14
Re: [Qemu-riscv] [Qemu-devel] [PULL 15/54] build: convert pci.mak to Kconfig
,
Paolo Bonzini
,
2019/03/14
Re: [Qemu-riscv] [Qemu-devel] [PULL 15/54] build: convert pci.mak to Kconfig
,
Michael S. Tsirkin
,
2019/03/14
Re: [Qemu-riscv] [Qemu-devel] [PULL 15/54] build: convert pci.mak to Kconfig
,
David Abdurachmanov
,
2019/03/14
Re: [Qemu-riscv] [Qemu-devel] [PULL 15/54] build: convert pci.mak to Kconfig
,
Paolo Bonzini
,
2019/03/14
Re: [Qemu-riscv] [Qemu-devel] [PULL 15/54] build: convert pci.mak to Kconfig
,
Markus Armbruster
,
2019/03/14
Re: [Qemu-riscv] [Qemu-devel] [PULL 15/54] build: convert pci.mak to Kconfig
,
Paolo Bonzini
,
2019/03/14
[Qemu-riscv] [PATCH v9 00/29] target/riscv: Convert to decodetree
,
Bastian Koppelmann
,
2019/03/13
[Qemu-riscv] [PATCH v9 18/29] target/riscv: Convert quadrant 2 of RVXC insns to decodetree
,
Bastian Koppelmann
,
2019/03/13
[Qemu-riscv] [PATCH v9 17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree
,
Bastian Koppelmann
,
2019/03/13
Re: [Qemu-riscv] [Qemu-devel] [PATCH] hw/riscv/virt: re-add machine-specific compatible string to /soc/ node
,
Bin Meng
,
2019/03/09
Re: [Qemu-riscv] [Qemu-devel] [PATCH] hw/riscv/virt: re-add machine-specific compatible string to /soc/ node
,
Auer, Lukas
,
2019/03/10
Re: [Qemu-riscv] [Qemu-devel] [PATCH] hw/riscv/virt: re-add machine-specific compatible string to /soc/ node
,
Bin Meng
,
2019/03/10
Re: [Qemu-riscv] [Qemu-devel] [PATCH] hw/riscv/virt: re-add machine-specific compatible string to /soc/ node
,
Auer, Lukas
,
2019/03/10
Re: [Qemu-riscv] [Qemu-devel] [PATCH] hw/riscv/virt: re-add machine-specific compatible string to /soc/ node
,
Bin Meng
,
2019/03/11
Re: [Qemu-riscv] [Qemu-devel] [PATCH] hw/riscv/virt: re-add machine-specific compatible string to /soc/ node
,
Auer, Lukas
,
2019/03/12
Re: [Qemu-riscv] [Qemu-devel] [PATCH] hw/riscv/virt: re-add machine-specific compatible string to /soc/ node
,
Bin Meng
,
2019/03/12
Re: [Qemu-riscv] [Qemu-devel] [PATCH] hw/riscv/virt: re-add machine-specific compatible string to /soc/ node
,
Auer, Lukas
,
2019/03/14
Re: [Qemu-riscv] [Qemu-devel] [PATCH] hw/riscv/virt: re-add machine-specific compatible string to /soc/ node
,
Bin Meng
,
2019/03/14
Re: [Qemu-riscv] [Qemu-devel] [PATCH] hw/riscv/virt: re-add machine-specific compatible string to /soc/ node
,
Auer, Lukas
,
2019/03/17
[Qemu-riscv] [PULL] target/riscv: Convert to decodetree
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 03/34] target/riscv: Convert RV32I load/store insns to decodetree
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 02/34] target/riscv: Convert RVXI branch insns to decodetree
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 04/34] target/riscv: Convert RV64I load/store insns to decodetree
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 01/34] target/riscv: Activate decodetree and implemnt LUI & AUIPC
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 05/34] target/riscv: Convert RVXI arithmetic insns to decodetree
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 06/34] target/riscv: Convert RVXI fence insns to decodetree
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 07/34] target/riscv: Convert RVXI csr insns to decodetree
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 10/34] target/riscv: Convert RV64A insns to decodetree
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 09/34] target/riscv: Convert RV32A insns to decodetree
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 08/34] target/riscv: Convert RVXM insns to decodetree
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 20/34] target/riscv: Remove manual decoding from gen_branch()
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 12/34] target/riscv: Convert RV64F insns to decodetree
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 24/34] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 15/34] target/riscv: Convert RV priv insns to decodetree
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 21/34] target/riscv: Remove manual decoding from gen_load()
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 22/34] target/riscv: Remove manual decoding from gen_store()
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 26/34] target/riscv: Remove manual decoding of RV32/64M insn
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 23/34] target/riscv: Move gen_arith_imm() decoding into trans_* functions
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 11/34] target/riscv: Convert RV32F insns to decodetree
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 29/34] target/riscv: Remove decode_RV32_64G()
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 25/34] target/riscv: Remove shift and slt insn manual decoding
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 19/34] target/riscv: Remove gen_jalr()
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 16/34] target/riscv: Convert quadrant 0 of RVXC insns to decodetree
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 14/34] target/riscv: Convert RV64D insns to decodetree
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 18/34] target/riscv: Convert quadrant 2 of RVXC insns to decodetree
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 17/34] target/riscv: Convert quadrant 1 of RVXC insns to decodetree
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 28/34] target/riscv: Remove gen_system()
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 30/34] target/riscv: Convert @cs_2 insns to share translation functions
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 13/34] target/riscv: Convert RV32D insns to decodetree
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 27/34] target/riscv: Rename trans_arith to gen_arith
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 31/34] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 32/34] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 33/34] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
,
Palmer Dabbelt
,
2019/03/01
[Qemu-riscv] [PULL 34/34] target/riscv: Remaining rvc insn reuse 32 bit translators
,
Palmer Dabbelt
,
2019/03/01
Re: [Qemu-riscv] [PULL] target/riscv: Convert to decodetree
,
Peter Maydell
,
2019/03/04
Re: [Qemu-riscv] [Qemu-devel] [PULL] target/riscv: Convert to decodetree
,
Bastian Koppelmann
,
2019/03/04
Re: [Qemu-riscv] [Qemu-devel] [PULL] target/riscv: Convert to decodetree
,
Bastian Koppelmann
,
2019/03/04
Re: [Qemu-riscv] [Qemu-devel] [PULL] target/riscv: Convert to decodetree
,
Richard Henderson
,
2019/03/04
Re: [Qemu-riscv] [Qemu-devel] [PULL] target/riscv: Convert to decodetree
,
Palmer Dabbelt
,
2019/03/04
[Qemu-riscv] [PULL] target/riscv: Convert to decodetree
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 26/29] target/riscv: Remove manual decoding of RV32/64M insn
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 29/29] target/riscv: Remove decode_RV32_64G()
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 28/29] target/riscv: Remove gen_system()
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 25/29] target/riscv: Remove shift and slt insn manual decoding
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 27/29] target/riscv: Rename trans_arith to gen_arith
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 21/29] target/riscv: Remove manual decoding from gen_load()
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 19/29] target/riscv: Remove gen_jalr()
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 20/29] target/riscv: Remove manual decoding from gen_branch()
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 22/29] target/riscv: Remove manual decoding from gen_store()
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 15/29] target/riscv: Convert RV priv insns to decodetree
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 18/29] target/riscv: Convert quadrant 2 of RVXC insns to decodetree
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 16/29] target/riscv: Convert quadrant 0 of RVXC insns to decodetree
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 14/29] target/riscv: Convert RV64D insns to decodetree
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 13/29] target/riscv: Convert RV32D insns to decodetree
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 11/29] target/riscv: Convert RV32F insns to decodetree
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 12/29] target/riscv: Convert RV64F insns to decodetree
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 06/29] target/riscv: Convert RVXI fence insns to decodetree
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 07/29] target/riscv: Convert RVXI csr insns to decodetree
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 08/29] target/riscv: Convert RVXM insns to decodetree
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 10/29] target/riscv: Convert RV64A insns to decodetree
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 09/29] target/riscv: Convert RV32A insns to decodetree
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 03/29] target/riscv: Convert RV32I load/store insns to decodetree
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 04/29] target/riscv: Convert RV64I load/store insns to decodetree
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 05/29] target/riscv: Convert RVXI arithmetic insns to decodetree
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 02/29] target/riscv: Convert RVXI branch insns to decodetree
,
Palmer Dabbelt
,
2019/03/12
[Qemu-riscv] [PULL 01/29] target/riscv: Activate decodetree and implemnt LUI & AUIPC
,
Palmer Dabbelt
,
2019/03/12
Re: [Qemu-riscv] [PULL] target/riscv: Convert to decodetree
,
Peter Maydell
,
2019/03/12
Re: [Qemu-riscv] [Qemu-devel] [PULL] target/riscv: Convert to decodetree
,
Bastian Koppelmann
,
2019/03/13
[Qemu-riscv] [PULL] target/riscv: Convert to decodetree
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 29/29] target/riscv: Remove decode_RV32_64G()
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 28/29] target/riscv: Remove gen_system()
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 26/29] target/riscv: Remove manual decoding of RV32/64M insn
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 21/29] target/riscv: Remove manual decoding from gen_load()
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 20/29] target/riscv: Remove manual decoding from gen_branch()
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 27/29] target/riscv: Rename trans_arith to gen_arith
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 25/29] target/riscv: Remove shift and slt insn manual decoding
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 16/29] target/riscv: Convert quadrant 0 of RVXC insns to decodetree
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree
,
Palmer Dabbelt
,
2019/03/13
Re: [Qemu-riscv] [Qemu-devel] [PULL 17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree
,
Alistair Francis
,
2019/03/14
Re: [Qemu-riscv] [Qemu-devel] [PULL 17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree
,
Palmer Dabbelt
,
2019/03/15
Re: [Qemu-riscv] [Qemu-devel] [PULL 17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree
,
Alistair Francis
,
2019/03/15
Re: [Qemu-riscv] [Qemu-devel] [PULL 17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree
,
Palmer Dabbelt
,
2019/03/15
Re: [Qemu-riscv] [Qemu-devel] [PULL 17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree
,
Bastian Koppelmann
,
2019/03/15
Re: [Qemu-riscv] [Qemu-devel] [PULL 17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree
,
Palmer Dabbelt
,
2019/03/15
Re: [Qemu-riscv] [Qemu-devel] [PULL 17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree
,
Palmer Dabbelt
,
2019/03/15
Re: [Qemu-riscv] [Qemu-devel] [PULL 17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree
,
Bastian Koppelmann
,
2019/03/15
Re: [Qemu-riscv] [Qemu-devel] [PULL 17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree
,
Bastian Koppelmann
,
2019/03/15
[Qemu-riscv] [PULL 22/29] target/riscv: Remove manual decoding from gen_store()
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 19/29] target/riscv: Remove gen_jalr()
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 15/29] target/riscv: Convert RV priv insns to decodetree
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 13/29] target/riscv: Convert RV32D insns to decodetree
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 18/29] target/riscv: Convert quadrant 2 of RVXC insns to decodetree
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 09/29] target/riscv: Convert RV32A insns to decodetree
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 11/29] target/riscv: Convert RV32F insns to decodetree
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 08/29] target/riscv: Convert RVXM insns to decodetree
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 14/29] target/riscv: Convert RV64D insns to decodetree
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 05/29] target/riscv: Convert RVXI arithmetic insns to decodetree
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 03/29] target/riscv: Convert RV32I load/store insns to decodetree
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 12/29] target/riscv: Convert RV64F insns to decodetree
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 10/29] target/riscv: Convert RV64A insns to decodetree
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 07/29] target/riscv: Convert RVXI csr insns to decodetree
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 06/29] target/riscv: Convert RVXI fence insns to decodetree
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 04/29] target/riscv: Convert RV64I load/store insns to decodetree
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 02/29] target/riscv: Convert RVXI branch insns to decodetree
,
Palmer Dabbelt
,
2019/03/13
[Qemu-riscv] [PULL 01/29] target/riscv: Activate decodetree and implemnt LUI & AUIPC
,
Palmer Dabbelt
,
2019/03/13
Re: [Qemu-riscv] [PULL] target/riscv: Convert to decodetree
,
Peter Maydell
,
2019/03/14
[
Prev Period
]
[
Next Period
]
Mail converted by
MHonArc