Re: [Qemu-riscv] [Qemu-devel] [PATCH 2/2] riscv: sifive_u: Correct UART0's IRQ in the device tree

[Alistair Francis]

On Sun, Mar 17, 2019 at 1:24 AM Bin Meng <address@hidden> wrote:
>
> The UART0's interrupt vector is wrongly set to 1 in the device tree.
> Use SIFIVE_U_UART0_IRQ instead.
>
> Signed-off-by: Bin Meng <address@hidden>

Reviewed-by: Alistair Francis <address@hidden>

Alistair

> ---
>
>  hw/riscv/sifive_u.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 7bc2582..57741c2 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -244,7 +244,7 @@ static void create_fdt(SiFiveUState *s, const struct 
> MemmapEntry *memmap,
>      qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
>                            SIFIVE_U_CLOCK_FREQ / 2);
>      qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
> -    qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1);
> +    qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
>
>      qemu_fdt_add_subnode(fdt, "/chosen");
>      qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
> --
> 2.7.4
>
>