[Qemu-riscv] [PATCH for-4.1 0/8] target/riscv: decodetree improvments

[Richard Henderson]

There's new support in decodetree for pattern groups.
I believe that patch 5, or something close to it, was
posted as an RFC as part of the original pattern group
patch set, but this cleans that up further.


r~


Richard Henderson (8):
  target/riscv: Name the argument sets for all of insn32 formats
  target/riscv: Use --static-decode for decodetree
  target/riscv: Merge argument sets for insn32 and insn16
  target/riscv: Merge argument decode for RVC shifti
  target/riscv: Use pattern groups in insn16.decode
  target/riscv: Split RVC32 and RVC64 insns into separate files
  target/riscv: Split gen_arith_imm into functional and temp
  target/riscv: Remove spaces from register names

 target/riscv/cpu.c                      |  16 +-
 target/riscv/insn_trans/trans_rvc.inc.c | 347 ------------------------
 target/riscv/insn_trans/trans_rvi.inc.c |  20 +-
 target/riscv/translate.c                |  40 ++-
 target/riscv/Makefile.objs              |  15 +-
 target/riscv/insn16-32.decode           |  28 ++
 target/riscv/insn16-64.decode           |  30 ++
 target/riscv/insn16.decode              | 154 ++++++-----
 target/riscv/insn32.decode              |  10 +-
 9 files changed, 205 insertions(+), 455 deletions(-)
 delete mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
 create mode 100644 target/riscv/insn16-32.decode
 create mode 100644 target/riscv/insn16-64.decode

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2.17.1