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[Qemu-riscv] [PATCH for-4.1 8/8] target/riscv: Remove spaces from regist
From: |
Richard Henderson |
Subject: |
[Qemu-riscv] [PATCH for-4.1 8/8] target/riscv: Remove spaces from register names |
Date: |
Mon, 1 Apr 2019 10:11:55 +0700 |
These extra spaces make the "-d op" dump look weird.
Signed-off-by: Richard Henderson <address@hidden>
---
target/riscv/cpu.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d61bce6d55..624528efb5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -29,17 +29,17 @@
static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
const char * const riscv_int_regnames[] = {
- "zero", "ra ", "sp ", "gp ", "tp ", "t0 ", "t1 ", "t2 ",
- "s0 ", "s1 ", "a0 ", "a1 ", "a2 ", "a3 ", "a4 ", "a5 ",
- "a6 ", "a7 ", "s2 ", "s3 ", "s4 ", "s5 ", "s6 ", "s7 ",
- "s8 ", "s9 ", "s10 ", "s11 ", "t3 ", "t4 ", "t5 ", "t6 "
+ "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2",
+ "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
+ "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7",
+ "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"
};
const char * const riscv_fpr_regnames[] = {
- "ft0 ", "ft1 ", "ft2 ", "ft3 ", "ft4 ", "ft5 ", "ft6 ", "ft7 ",
- "fs0 ", "fs1 ", "fa0 ", "fa1 ", "fa2 ", "fa3 ", "fa4 ", "fa5 ",
- "fa6 ", "fa7 ", "fs2 ", "fs3 ", "fs4 ", "fs5 ", "fs6 ", "fs7 ",
- "fs8 ", "fs9 ", "fs10", "fs11", "ft8 ", "ft9 ", "ft10", "ft11"
+ "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",
+ "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
+ "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
+ "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
};
const char * const riscv_excp_names[] = {
--
2.17.1
- [Qemu-riscv] [PATCH for-4.1 0/8] target/riscv: decodetree improvments, Richard Henderson, 2019/03/31
- [Qemu-riscv] [PATCH for-4.1 1/8] target/riscv: Name the argument sets for all of insn32 formats, Richard Henderson, 2019/03/31
- [Qemu-riscv] [PATCH for-4.1 2/8] target/riscv: Use --static-decode for decodetree, Richard Henderson, 2019/03/31
- [Qemu-riscv] [PATCH for-4.1 4/8] target/riscv: Merge argument decode for RVC shifti, Richard Henderson, 2019/03/31
- [Qemu-riscv] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16, Richard Henderson, 2019/03/31
- [Qemu-riscv] [PATCH for-4.1 5/8] target/riscv: Use pattern groups in insn16.decode, Richard Henderson, 2019/03/31
- [Qemu-riscv] [PATCH for-4.1 6/8] target/riscv: Split RVC32 and RVC64 insns into separate files, Richard Henderson, 2019/03/31
- [Qemu-riscv] [PATCH for-4.1 7/8] target/riscv: Split gen_arith_imm into functional and temp, Richard Henderson, 2019/03/31
- [Qemu-riscv] [PATCH for-4.1 8/8] target/riscv: Remove spaces from register names,
Richard Henderson <=