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[Qemu-riscv] [PATCH v1 10/12] RISC-V: Update load reservation comment in
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [PATCH v1 10/12] RISC-V: Update load reservation comment in do_interrupt |
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Date: |
Sat, 16 Mar 2019 01:21:21 +0000 |
From: Michael Clark <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu_helper.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 6d3fbc3401..b17f169681 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -525,7 +525,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
riscv_cpu_set_mode(env, PRV_M);
}
- /* TODO yield load reservation */
+
+ /* NOTE: it is not necessary to yield load reservations here. It is only
+ * necessary for an SC from "another hart" to cause a load reservation
+ * to be yielded. Refer to the memory consistency model section of the
+ * RISC-V ISA Specification.
+ */
+
#endif
cs->exception_index = EXCP_NONE; /* mark handled to qemu */
}
--
2.21.0
- [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4, Alistair Francis, 2019/03/15
- [Qemu-riscv] [PATCH v1 11/12] riscv: sifive_u: Allow up to 4 CPUs to be created, Alistair Francis, 2019/03/15
- [Qemu-riscv] [PATCH v1 12/12] target/riscv: Remove unused struct, Alistair Francis, 2019/03/15
- [Qemu-riscv] [PATCH v1 10/12] RISC-V: Update load reservation comment in do_interrupt,
Alistair Francis <=
- [Qemu-riscv] [PATCH v1 07/12] RISC-V: Change local interrupts from edge to level, Alistair Francis, 2019/03/15
- [Qemu-riscv] [PATCH v1 09/12] RISC-V: Convert trap debugging to trace events, Alistair Francis, 2019/03/15
- [Qemu-riscv] [PATCH v1 08/12] RISC-V: Add support for vectored interrupts, Alistair Francis, 2019/03/15
- [Qemu-riscv] [PATCH v1 06/12] RISC-V: linux-user support for RVE ABI, Alistair Francis, 2019/03/15
- [Qemu-riscv] [PATCH v1 05/12] elf: Add RISC-V PSABI ELF header defines, Alistair Francis, 2019/03/15
- [Qemu-riscv] [PATCH v1 03/12] RISC-V: Allow interrupt controllers to claim interrupts, Alistair Francis, 2019/03/15
- [Qemu-riscv] [PATCH v1 01/12] riscv: pmp: Log pmp access errors as guest errors, Alistair Francis, 2019/03/15
- [Qemu-riscv] [PATCH v1 04/12] RISC-V: Remove unnecessary disassembler constraints, Alistair Francis, 2019/03/15
- [Qemu-riscv] [PATCH v1 02/12] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC, Alistair Francis, 2019/03/15