Re: [Qemu-riscv] [PATCH for 4.0 v1 0/5] Update the QEMU PLIC addresses

[Palmer Dabbelt]

On Tue, 26 Mar 2019 15:19:25 PDT (-0700), address@hidden wrote:
> On Wed, Mar 20, 2019 at 5:45 PM Alistair Francis
> <address@hidden> wrote:
> > This series updates the PLIC address to match the documentation.
> >
> > This fixes: https://github.com/riscv/opensbi/issues/97
> >
> > Alistair Francis (5):
> >   riscv: plic: Fix incorrect irq calculation
> >   riscv: sifive_u: Fix PLIC priority base offset and numbering
> >   riscv: sifive_e: Fix PLIC priority base offset
> >   riscv: virt: Fix PLIC priority base offset
> >   riscv: plic: Log guest errors
>
> Ping! Can this make it into 4.0?

Sorry, I missed this one.  I'll take a look.

> Alistair
>
> >  hw/riscv/sifive_plic.c      | 16 +++++++++++-----
> >  hw/riscv/sifive_u.c         |  2 +-
> >  include/hw/riscv/sifive_e.h |  2 +-
> >  include/hw/riscv/sifive_u.h |  4 ++--
> >  include/hw/riscv/virt.h     |  2 +-
> >  5 files changed, 16 insertions(+), 10 deletions(-)
> >
> > --
> > 2.21.0