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[Qemu-riscv] [PULL 10/19] elf: Add RISC-V PSABI ELF header defines
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 10/19] elf: Add RISC-V PSABI ELF header defines |
Date: |
Tue, 19 Mar 2019 05:47:54 -0700 |
From: Michael Clark <address@hidden>
Refer to the RISC-V PSABI specification for details:
- https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
Cc: Michael Tokarev <address@hidden>
Cc: Richard Henderson <address@hidden>
Cc: Alistair Francis <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
include/elf.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index b35347eee767..ea7708a4ea9a 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -1393,6 +1393,16 @@ typedef struct {
#define R_RISCV_SET16 55
#define R_RISCV_SET32 56
+/* RISC-V ELF Flags. */
+#define EF_RISCV_RVC 0x0001
+#define EF_RISCV_FLOAT_ABI 0x0006
+#define EF_RISCV_FLOAT_ABI_SOFT 0x0000
+#define EF_RISCV_FLOAT_ABI_SINGLE 0x0002
+#define EF_RISCV_FLOAT_ABI_DOUBLE 0x0004
+#define EF_RISCV_FLOAT_ABI_QUAD 0x0006
+#define EF_RISCV_RVE 0x0008
+#define EF_RISCV_TSO 0x0010
+
typedef struct elf32_rel {
Elf32_Addr r_offset;
Elf32_Word r_info;
--
2.19.2
- [Qemu-riscv] [PULL 06/19] riscv: pmp: Log pmp access errors as guest errors, (continued)
- [Qemu-riscv] [PULL 06/19] riscv: pmp: Log pmp access errors as guest errors, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 19/19] riscv: sifive_u: Correct UART0's IRQ in the device tree, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 18/19] riscv: sifive_uart: Generate TX interrupt, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 17/19] target/riscv: Remove unused struct, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 16/19] riscv: sifive_u: Allow up to 4 CPUs to be created, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 15/19] RISC-V: Update load reservation comment in do_interrupt, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 14/19] RISC-V: Convert trap debugging to trace events, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 13/19] RISC-V: Add support for vectored interrupts, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 12/19] RISC-V: Change local interrupts from edge to level, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 11/19] RISC-V: linux-user support for RVE ABI, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 10/19] elf: Add RISC-V PSABI ELF header defines,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 09/19] RISC-V: Remove unnecessary disassembler constraints, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 05/19] RISC-V: Add hooks to use the gdb xml files., Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 07/19] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 08/19] RISC-V: Allow interrupt controllers to claim interrupts, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 04/19] RISC-V: Add debug support for accessing CSRs., Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 03/19] RISC-V: Fixes to CSR_* register macros., Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 02/19] RISC-V: Add 64-bit gdb xml files., Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 01/19] RISC-V: Add 32-bit gdb xml files., Palmer Dabbelt, 2019/03/19
- Re: [Qemu-riscv] [PULL] RISC-V Patches for 4.0-rc0, Part 2, Peter Maydell, 2019/03/19