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[Qemu-riscv] [PULL 06/19] riscv: pmp: Log pmp access errors as guest err
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 06/19] riscv: pmp: Log pmp access errors as guest errors |
Date: |
Tue, 19 Mar 2019 05:47:50 -0700 |
From: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/pmp.c | 20 +++++++++++++-------
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 15a5366616bd..b11c4ae22fbc 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -113,10 +113,11 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t
pmp_index, uint8_t val)
env->pmp_state.pmp[pmp_index].cfg_reg = val;
pmp_update_rule(env, pmp_index);
} else {
- PMP_DEBUG("ignoring write - locked");
+ qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
}
} else {
- PMP_DEBUG("ignoring write - out of bounds");
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "ignoring pmpcfg write - out of bounds\n");
}
}
@@ -249,7 +250,8 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong
addr,
/* partially inside */
if ((s + e) == 1) {
- PMP_DEBUG("pmp violation - access is partially inside");
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "pmp violation - access is partially inside\n");
ret = 0;
break;
}
@@ -306,7 +308,8 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t
reg_index,
env->mhartid, reg_index, val);
if ((reg_index & 1) && (sizeof(target_ulong) == 8)) {
- PMP_DEBUG("ignoring write - incorrect address");
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "ignoring pmpcfg write - incorrect address\n");
return;
}
@@ -353,10 +356,12 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t
addr_index,
env->pmp_state.pmp[addr_index].addr_reg = val;
pmp_update_rule(env, addr_index);
} else {
- PMP_DEBUG("ignoring write - locked");
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "ignoring pmpaddr write - locked\n");
}
} else {
- PMP_DEBUG("ignoring write - out of bounds");
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "ignoring pmpaddr write - out of bounds\n");
}
}
@@ -372,7 +377,8 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t
addr_index)
if (addr_index < MAX_RISCV_PMPS) {
return env->pmp_state.pmp[addr_index].addr_reg;
} else {
- PMP_DEBUG("ignoring read - out of bounds");
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "ignoring pmpaddr read - out of bounds\n");
return 0;
}
}
--
2.19.2
- [Qemu-riscv] [PULL] RISC-V Patches for 4.0-rc0, Part 2, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 06/19] riscv: pmp: Log pmp access errors as guest errors,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 19/19] riscv: sifive_u: Correct UART0's IRQ in the device tree, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 18/19] riscv: sifive_uart: Generate TX interrupt, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 17/19] target/riscv: Remove unused struct, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 16/19] riscv: sifive_u: Allow up to 4 CPUs to be created, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 15/19] RISC-V: Update load reservation comment in do_interrupt, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 14/19] RISC-V: Convert trap debugging to trace events, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 13/19] RISC-V: Add support for vectored interrupts, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 12/19] RISC-V: Change local interrupts from edge to level, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 11/19] RISC-V: linux-user support for RVE ABI, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 10/19] elf: Add RISC-V PSABI ELF header defines, Palmer Dabbelt, 2019/03/19