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[Qemu-riscv] [PULL 22/29] target/riscv: Remove manual decoding from gen_
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 22/29] target/riscv: Remove manual decoding from gen_store() |
Date: |
Tue, 12 Mar 2019 06:15:19 -0700 |
From: Bastian Koppelmann <address@hidden>
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_store() did.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/insn_trans/trans_rvi.inc.c | 27 +++++++++++++++++--------
target/riscv/translate.c | 8 +++++---
2 files changed, 24 insertions(+), 11 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c
b/target/riscv/insn_trans/trans_rvi.inc.c
index cc361ed4d151..5a09c6335ae0 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -168,22 +168,34 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
return gen_load(ctx, a, MO_TEUW);
}
-static bool trans_sb(DisasContext *ctx, arg_sb *a)
+static bool gen_store(DisasContext *ctx, arg_sb *a, TCGMemOp memop)
{
- gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm);
+ TCGv t0 = tcg_temp_new();
+ TCGv dat = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_get_gpr(dat, a->rs2);
+
+ tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
+ tcg_temp_free(t0);
+ tcg_temp_free(dat);
return true;
}
+
+static bool trans_sb(DisasContext *ctx, arg_sb *a)
+{
+ return gen_store(ctx, a, MO_SB);
+}
+
static bool trans_sh(DisasContext *ctx, arg_sh *a)
{
- gen_store(ctx, OPC_RISC_SH, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_store(ctx, a, MO_TESW);
}
static bool trans_sw(DisasContext *ctx, arg_sw *a)
{
- gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_store(ctx, a, MO_TESL);
}
#ifdef TARGET_RISCV64
@@ -199,8 +211,7 @@ static bool trans_ld(DisasContext *ctx, arg_ld *a)
static bool trans_sd(DisasContext *ctx, arg_sd *a)
{
- gen_store(ctx, OPC_RISC_SD, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_store(ctx, a, MO_TEQ);
}
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 99d6d3b4ae91..cdc08b1bff20 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -56,6 +56,7 @@ typedef struct DisasContext {
int frm;
} DisasContext;
+#ifdef TARGET_RISCV64
/* convert riscv funct3 to qemu memop for load/store */
static const int tcg_memop_lookup[8] = {
[0 ... 7] = -1,
@@ -69,6 +70,7 @@ static const int tcg_memop_lookup[8] = {
[6] = MO_TEUL,
#endif
};
+#endif
#ifdef TARGET_RISCV64
#define CASE_OP_32_64(X) case X: case glue(X, W)
@@ -551,9 +553,8 @@ static void gen_load_c(DisasContext *ctx, uint32_t opc, int
rd, int rs1,
tcg_temp_free(t0);
tcg_temp_free(t1);
}
-#endif
-static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
+static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
target_long imm)
{
TCGv t0 = tcg_temp_new();
@@ -572,6 +573,7 @@ static void gen_store(DisasContext *ctx, uint32_t opc, int
rs1, int rs2,
tcg_temp_free(t0);
tcg_temp_free(dat);
}
+#endif
#ifndef CONFIG_USER_ONLY
/* The states of mstatus_fs are:
@@ -736,7 +738,7 @@ static void decode_RV32_64C0(DisasContext *ctx)
case 7:
#if defined(TARGET_RISCV64)
/* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
- gen_store(ctx, OPC_RISC_SD, rs1s, rd_rs2,
+ gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
GET_C_LD_IMM(ctx->opcode));
#else
/* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
--
2.19.2
- [Qemu-riscv] [PULL 26/29] target/riscv: Remove manual decoding of RV32/64M insn, (continued)
- [Qemu-riscv] [PULL 26/29] target/riscv: Remove manual decoding of RV32/64M insn, Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 29/29] target/riscv: Remove decode_RV32_64G(), Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 28/29] target/riscv: Remove gen_system(), Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 25/29] target/riscv: Remove shift and slt insn manual decoding, Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 27/29] target/riscv: Rename trans_arith to gen_arith, Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 21/29] target/riscv: Remove manual decoding from gen_load(), Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 19/29] target/riscv: Remove gen_jalr(), Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 20/29] target/riscv: Remove manual decoding from gen_branch(), Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 22/29] target/riscv: Remove manual decoding from gen_store(),
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 15/29] target/riscv: Convert RV priv insns to decodetree, Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 18/29] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 16/29] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 14/29] target/riscv: Convert RV64D insns to decodetree, Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree, Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 13/29] target/riscv: Convert RV32D insns to decodetree, Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 11/29] target/riscv: Convert RV32F insns to decodetree, Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 12/29] target/riscv: Convert RV64F insns to decodetree, Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 06/29] target/riscv: Convert RVXI fence insns to decodetree, Palmer Dabbelt, 2019/03/12
- [Qemu-riscv] [PULL 07/29] target/riscv: Convert RVXI csr insns to decodetree, Palmer Dabbelt, 2019/03/12