Re: [Simulavr-devel] test mechanism

[address@hidden]

On Wed Aug 19  8:15 , "address@hidden"  sent:

>On Tue Aug 18 13:38 , "address@hidden"  sent:
>
>>On Tue Aug 18 11:47 , ThomasK address@hidden> sent:
>
>>>Behaviour in simulavr is now like in M128, means read complete byte, 
>>>modify, write complete byte. For the new behaviour we need a new 
>>>interface for IO registers, one is clearBit(bitnum), the other 
>>>setBit(bitnum), not only read byte: operator char() and write byte: 
>>>operator=. And then, of course, for all the hardware units, which have 
>>>to provide this, not only a get and set method, but also a getbit/setbit 
>>>method or other modifybit(bitval, bitnum).
>>
>>I'd use the names sbi and cbi.

One more time, and more detail:

decoder.h :
class avr_op_CBI:public DecodedInstruction
{
...
    public:
        avr_op_CBI (word opcode, AvrDevice *c);
        int operator()() { ioreg.cbi(K); return 2; }
        int Trace();
...
};


class avr_op_SBI:public DecodedInstruction
{
...
    public:
        avr_op_SBI (word opcode, AvrDevice *c);
        int operator()() { ioreg.sbi(K); return 2; }
        int Trace();
...
};

rwmemm.h :
class RWMemoryMembers {
...
        virtual unsigned char operator=(unsigned char val) =0;
#ifndef SWIG
        virtual operator unsigned char() const =0 ;

        // sbi and cbi will need to be overridden for some newer registers
        // each mask has exactly one bit set
        virtual void sbi(unsigned char mask) { *this= *this |  mask; }
        virtual void cbi(unsigned char mask) { *this= *this & ~mask; }
#endif
...
};

I don't understand the need for #ifndef SWIG .


--
Michael Hennebry
address@hidden
"War is only a hobby."

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