Re: [Simulavr-devel] test mechanism

[address@hidden]

Thomas,

I added the list to the To: field.

On Tue Aug 18 11:47 , ThomasK <address@hidden> sent:

>now I know, what you mean. It took a little bit time on me. ;-) Yes, 
>that's a real core change, which changes the behaviour of CBI and SBI. A 
>feature, that can make people unlucky!
>
>It looks so, that newer AVR cores (and devices) have this, 
>M48/88/168/328 and also M164/324/644 and Tiny2313 and so one.
>
>Behaviour in simulavr is now like in M128, means read complete byte, 
>modify, write complete byte. For the new behaviour we need a new 
>interface for IO registers, one is clearBit(bitnum), the other 
>setBit(bitnum), not only read byte: operator char() and write byte: 
>operator=. And then, of course, for all the hardware units, which have 
>to provide this, not only a get and set method, but also a getbit/setbit 
>method or other modifybit(bitval, bitnum).

I'd use the names sbi and cbi.

>And a flag for the core to signal old/new behaviour.

We might not have to put a flag in the core.
We just have to make hardware units differ depending on the SBI and CBI 
behavior.
For the most part, using byte-size chunks will work.
It's only the registers that have non-obvious
semantics that will need to be special.
IIRC the SBI and CBI instructions currently read and writer register bytes
using the same mechanism as for IN, OUT, LDD and LDS.
That will need to change to invoking sbi and cbi methods on the registers.

>All together a "nice" piece of work ... ;-)
>
>Question at all: do we have also some other "nice" features, which 
>change the behaviour of core?

There are some registers that affect flags by being read,
but I think those are out of the range of SBI, CBI, SBIC and SBIS.

--
Michael Hennebry
address@hidden
"War is only a hobby."

---- Msg sent via CableONE.net MyMail - http://www.cableone.net