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[PATCH 10/13] accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull
From: |
Richard Henderson |
Subject: |
[PATCH 10/13] accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull |
Date: |
Thu, 23 Feb 2023 10:43:39 -1000 |
Allow the target to set tlb flags to apply to all of the
comparators. Remove MemTxAttrs.byte_swap, as the bit is
not relevant to memory transactions, only the page mapping.
Adjust target/sparc to set TLB_BSWAP directly.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-defs.h | 3 +++
include/exec/memattrs.h | 2 --
accel/tcg/cputlb.c | 5 +----
target/sparc/mmu_helper.c | 2 +-
4 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index ef10c625d4..53743ff3f2 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -170,6 +170,9 @@ typedef struct CPUTLBEntryFull {
/* @lg_page_size contains the log2 of the page size. */
uint8_t lg_page_size;
+ /* Additional tlb flags requested by tlb_fill. */
+ uint8_t tlb_fill_flags;
+
/*
* Additional tlb flags for use by the slow path. If non-zero,
* the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW.
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index 1bd7b6c5ca..5300649c8c 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -45,8 +45,6 @@ typedef struct MemTxAttrs {
unsigned int memory:1;
/* Requester ID (for MSI for example) */
unsigned int requester_id:16;
- /* Invert endianness for this page */
- unsigned int byte_swap:1;
} MemTxAttrs;
/* Bus masters which don't specify any attributes will get this,
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index cc98df9517..a90688ac30 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1168,14 +1168,11 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx,
" prot=%x idx=%d\n",
vaddr, full->phys_addr, prot, mmu_idx);
- read_flags = 0;
+ read_flags = full->tlb_fill_flags;
if (full->lg_page_size < TARGET_PAGE_BITS) {
/* Repeat the MMU check and TLB fill on every access. */
read_flags |= TLB_INVALID_MASK;
}
- if (full->attrs.byte_swap) {
- read_flags |= TLB_BSWAP;
- }
is_ram = memory_region_is_ram(section->mr);
is_romd = memory_region_is_romd(section->mr);
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index a98dd0abd4..fa58b4dc03 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -580,7 +580,7 @@ static int get_physical_address_data(CPUSPARCState *env,
CPUTLBEntryFull *full,
int do_fault = 0;
if (TTE_IS_IE(env->dtlb[i].tte)) {
- full->attrs.byte_swap = true;
+ full->tlb_fill_flags |= TLB_BSWAP;
}
/* access ok? */
--
2.34.1
- [PATCH 02/13] accel/tcg: Retain prot flags from tlb_fill, (continued)
- [PATCH 02/13] accel/tcg: Retain prot flags from tlb_fill, Richard Henderson, 2023/02/23
- [PATCH 03/13] accel/tcg: Store some tlb flags in CPUTLBEntryFull, Richard Henderson, 2023/02/23
- [PATCH 04/13] accel/tcg: Honor TLB_DISCARD_WRITE in atomic_mmu_lookup, Richard Henderson, 2023/02/23
- [PATCH 05/13] softmmu/physmem: Check watchpoints for read+write at once, Richard Henderson, 2023/02/23
- [PATCH 06/13] accel/tcg: Trigger watchpoints from atomic_mmu_lookup, Richard Henderson, 2023/02/23
- [PATCH 07/13] accel/tcg: Move TLB_WATCHPOINT to TLB_SLOW_FLAGS_MASK, Richard Henderson, 2023/02/23
- [PATCH 08/13] target/arm: Support 32-byte alignment in pow2_align, Richard Henderson, 2023/02/23
- [PATCH 09/13] exec/memattrs: Remove target_tlb_bit*, Richard Henderson, 2023/02/23
- [PATCH 10/13] accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull,
Richard Henderson <=
- [PATCH 11/13] accel/tcg: Add TLB_CHECK_ALIGNED, Richard Henderson, 2023/02/23
- [PATCH 12/13] target/arm: Do memory type alignment check when translation disabled, Richard Henderson, 2023/02/23
- [PATCH 13/13] target/arm: Do memory type alignment check when translation enabled, Richard Henderson, 2023/02/23