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[PATCH 05/13] softmmu/physmem: Check watchpoints for read+write at once
From: |
Richard Henderson |
Subject: |
[PATCH 05/13] softmmu/physmem: Check watchpoints for read+write at once |
Date: |
Thu, 23 Feb 2023 10:43:34 -1000 |
Atomic operations are read-modify-write, and we'd like to
be able to test both read and write with one call. This is
easy enough, with BP_MEM_READ | BP_MEM_WRITE.
Add BP_HIT_SHIFT to make it easy to set BP_WATCHPOINT_HIT_*.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 7 ++++---
softmmu/physmem.c | 19 ++++++++++---------
2 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 2417597236..2f85ba14b3 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -921,9 +921,10 @@ void cpu_single_step(CPUState *cpu, int enabled);
#define BP_GDB 0x10
#define BP_CPU 0x20
#define BP_ANY (BP_GDB | BP_CPU)
-#define BP_WATCHPOINT_HIT_READ 0x40
-#define BP_WATCHPOINT_HIT_WRITE 0x80
-#define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE)
+#define BP_HIT_SHIFT 6
+#define BP_WATCHPOINT_HIT_READ (BP_MEM_READ << BP_HIT_SHIFT)
+#define BP_WATCHPOINT_HIT_WRITE (BP_MEM_WRITE << BP_HIT_SHIFT)
+#define BP_WATCHPOINT_HIT (BP_MEM_ACCESS << BP_HIT_SHIFT)
int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
CPUBreakpoint **breakpoint);
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index cb998cdf23..c4f62dee60 100644
--- a/softmmu/physmem.c
+++ b/softmmu/physmem.c
@@ -915,9 +915,12 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr
len,
/* this is currently used only by ARM BE32 */
addr = cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len);
}
+
+ assert((flags & ~BP_MEM_ACCESS) == 0);
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
- if (watchpoint_address_matches(wp, addr, len)
- && (wp->flags & flags)) {
+ int hit_flags = wp->flags & flags;
+
+ if (hit_flags && watchpoint_address_matches(wp, addr, len)) {
if (replay_running_debug()) {
/*
* replay_breakpoint reads icount.
@@ -936,16 +939,14 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr,
vaddr len,
replay_breakpoint();
return;
}
- if (flags == BP_MEM_READ) {
- wp->flags |= BP_WATCHPOINT_HIT_READ;
- } else {
- wp->flags |= BP_WATCHPOINT_HIT_WRITE;
- }
+
+ wp->flags |= hit_flags << BP_HIT_SHIFT;
wp->hitaddr = MAX(addr, wp->vaddr);
wp->hitattrs = attrs;
- if (wp->flags & BP_CPU && cc->tcg_ops->debug_check_watchpoint &&
- !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) {
+ if (wp->flags & BP_CPU
+ && cc->tcg_ops->debug_check_watchpoint
+ && !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) {
wp->flags &= ~BP_WATCHPOINT_HIT;
continue;
}
--
2.34.1
- [PATCH 00/13] {tcg,aarch64}: Add TLB_CHECK_ALIGNED, Richard Henderson, 2023/02/23
- [PATCH 01/13] target/sparc: Use tlb_set_page_full, Richard Henderson, 2023/02/23
- [PATCH 02/13] accel/tcg: Retain prot flags from tlb_fill, Richard Henderson, 2023/02/23
- [PATCH 03/13] accel/tcg: Store some tlb flags in CPUTLBEntryFull, Richard Henderson, 2023/02/23
- [PATCH 04/13] accel/tcg: Honor TLB_DISCARD_WRITE in atomic_mmu_lookup, Richard Henderson, 2023/02/23
- [PATCH 05/13] softmmu/physmem: Check watchpoints for read+write at once,
Richard Henderson <=
- [PATCH 06/13] accel/tcg: Trigger watchpoints from atomic_mmu_lookup, Richard Henderson, 2023/02/23
- [PATCH 07/13] accel/tcg: Move TLB_WATCHPOINT to TLB_SLOW_FLAGS_MASK, Richard Henderson, 2023/02/23
- [PATCH 08/13] target/arm: Support 32-byte alignment in pow2_align, Richard Henderson, 2023/02/23
- [PATCH 09/13] exec/memattrs: Remove target_tlb_bit*, Richard Henderson, 2023/02/23
- [PATCH 10/13] accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull, Richard Henderson, 2023/02/23
- [PATCH 11/13] accel/tcg: Add TLB_CHECK_ALIGNED, Richard Henderson, 2023/02/23
- [PATCH 12/13] target/arm: Do memory type alignment check when translation disabled, Richard Henderson, 2023/02/23