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[PATCH 06/13] accel/tcg: Trigger watchpoints from atomic_mmu_lookup
From: |
Richard Henderson |
Subject: |
[PATCH 06/13] accel/tcg: Trigger watchpoints from atomic_mmu_lookup |
Date: |
Thu, 23 Feb 2023 10:43:35 -1000 |
Fixes a bug in that we weren't reporting these changes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/cputlb.c | 40 +++++++++++++++++++++++++++++-----------
1 file changed, 29 insertions(+), 11 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 74ad8e0876..e0765c8c10 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1908,6 +1908,7 @@ static void *atomic_mmu_lookup(CPUArchState *env,
target_ulong addr,
CPUTLBEntry *tlbe;
target_ulong tlb_addr;
void *hostaddr;
+ CPUTLBEntryFull *full;
tcg_debug_assert(mmu_idx < NB_MMU_MODES);
@@ -1947,17 +1948,26 @@ static void *atomic_mmu_lookup(CPUArchState *env,
target_ulong addr,
tlb_addr = tlb_addr_write(tlbe) & ~TLB_INVALID_MASK;
}
- /* Let the guest notice RMW on a write-only page. */
- if ((prot & PAGE_READ) &&
- unlikely(tlbe->addr_read != (tlb_addr & ~TLB_NOTDIRTY))) {
- tlb_fill(env_cpu(env), addr, size,
- MMU_DATA_LOAD, mmu_idx, retaddr);
+ if (prot & PAGE_READ) {
/*
- * Since we don't support reads and writes to different addresses,
- * and we do have the proper page loaded for write, this shouldn't
- * ever return. But just in case, handle via stop-the-world.
+ * Let the guest notice RMW on a write-only page.
+ * We have just verified that the page is writable.
+ * Subpage lookups may have left TLB_INVALID_MASK set,
+ * but addr_read will only be -1 if PAGE_READ was unset.
*/
- goto stop_the_world;
+ if (unlikely(tlbe->addr_read == -1)) {
+ tlb_fill(env_cpu(env), addr, size,
+ MMU_DATA_LOAD, mmu_idx, retaddr);
+ /*
+ * Since we don't support reads and writes to different
+ * addresses, and we do have the proper page loaded for
+ * write, this shouldn't ever return. But just in case,
+ * handle via stop-the-world.
+ */
+ goto stop_the_world;
+ }
+ /* Collect TLB_WATCHPOINT for read. */
+ tlb_addr |= tlbe->addr_read;
}
} else /* if (prot & PAGE_READ) */ {
tlb_addr = tlbe->addr_read;
@@ -1981,10 +1991,18 @@ static void *atomic_mmu_lookup(CPUArchState *env,
target_ulong addr,
}
hostaddr = (void *)((uintptr_t)addr + tlbe->addend);
+ full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
if (unlikely(tlb_addr & TLB_NOTDIRTY)) {
- notdirty_write(env_cpu(env), addr, size,
- &env_tlb(env)->d[mmu_idx].fulltlb[index], retaddr);
+ notdirty_write(env_cpu(env), addr, size, full, retaddr);
+ }
+
+ if (unlikely(tlb_addr & TLB_WATCHPOINT)) {
+ QEMU_BUILD_BUG_ON(PAGE_READ != BP_MEM_READ);
+ QEMU_BUILD_BUG_ON(PAGE_WRITE != BP_MEM_WRITE);
+ /* therefore prot == watchpoint bits */
+ cpu_check_watchpoint(env_cpu(env), addr, size,
+ full->attrs, prot, retaddr);
}
return hostaddr;
--
2.34.1
- [PATCH 00/13] {tcg,aarch64}: Add TLB_CHECK_ALIGNED, Richard Henderson, 2023/02/23
- [PATCH 01/13] target/sparc: Use tlb_set_page_full, Richard Henderson, 2023/02/23
- [PATCH 02/13] accel/tcg: Retain prot flags from tlb_fill, Richard Henderson, 2023/02/23
- [PATCH 03/13] accel/tcg: Store some tlb flags in CPUTLBEntryFull, Richard Henderson, 2023/02/23
- [PATCH 04/13] accel/tcg: Honor TLB_DISCARD_WRITE in atomic_mmu_lookup, Richard Henderson, 2023/02/23
- [PATCH 05/13] softmmu/physmem: Check watchpoints for read+write at once, Richard Henderson, 2023/02/23
- [PATCH 06/13] accel/tcg: Trigger watchpoints from atomic_mmu_lookup,
Richard Henderson <=
- [PATCH 07/13] accel/tcg: Move TLB_WATCHPOINT to TLB_SLOW_FLAGS_MASK, Richard Henderson, 2023/02/23
- [PATCH 08/13] target/arm: Support 32-byte alignment in pow2_align, Richard Henderson, 2023/02/23
- [PATCH 09/13] exec/memattrs: Remove target_tlb_bit*, Richard Henderson, 2023/02/23
- [PATCH 10/13] accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull, Richard Henderson, 2023/02/23
- [PATCH 11/13] accel/tcg: Add TLB_CHECK_ALIGNED, Richard Henderson, 2023/02/23
- [PATCH 12/13] target/arm: Do memory type alignment check when translation disabled, Richard Henderson, 2023/02/23
- [PATCH 13/13] target/arm: Do memory type alignment check when translation enabled, Richard Henderson, 2023/02/23