[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 09/21] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root}
From: |
Richard Henderson |
Subject: |
[PATCH v2 09/21] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root} |
Date: |
Mon, 20 Feb 2023 13:26:14 -1000 |
With FEAT_RME, there are four physical address spaces.
For now, just define the symbols, and mention them in
the same spots as the other Phys indexes in ptw.c.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu-param.h | 2 +-
target/arm/cpu.h | 23 +++++++++++++++++++++--
target/arm/ptw.c | 10 ++++++++--
3 files changed, 30 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index 53cac9c89b..8dfd7a0bb6 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -47,6 +47,6 @@
bool guarded;
#endif
-#define NB_MMU_MODES 12
+#define NB_MMU_MODES 14
#endif
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c9585390d4..4bafe8340e 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2864,8 +2864,10 @@ typedef enum ARMMMUIdx {
ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A,
/* TLBs with 1-1 mapping to the physical address spaces. */
- ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A,
- ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A,
+ ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A,
+ ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A,
+ ARMMMUIdx_Phys_Root = 12 | ARM_MMU_IDX_A,
+ ARMMMUIdx_Phys_Realm = 13 | ARM_MMU_IDX_A,
/*
* These are not allocated TLBs and are used only for AT system
@@ -2929,6 +2931,23 @@ typedef enum ARMASIdx {
ARMASIdx_TagS = 3,
} ARMASIdx;
+static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space)
+{
+ /* Assert the relative order of the physical mmu indexes. */
+ QEMU_BUILD_BUG_ON(ARMSS_Secure != 0);
+ QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure);
+ QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root);
+ QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm);
+
+ return ARMMMUIdx_Phys_S + space;
+}
+
+static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx)
+{
+ assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm);
+ return idx - ARMMMUIdx_Phys_S;
+}
+
static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
{
/* If all the CLIDR.Ctypem bits are 0 there are no caches, and
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 5ed5bb5039..5a0c5edc88 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -182,8 +182,10 @@ static bool regime_translation_disabled(CPUARMState *env,
ARMMMUIdx mmu_idx,
case ARMMMUIdx_E3:
break;
- case ARMMMUIdx_Phys_NS:
case ARMMMUIdx_Phys_S:
+ case ARMMMUIdx_Phys_NS:
+ case ARMMMUIdx_Phys_Root:
+ case ARMMMUIdx_Phys_Realm:
/* No translation for physical address spaces. */
return true;
@@ -2632,8 +2634,10 @@ static bool get_phys_addr_disabled(CPUARMState *env,
target_ulong address,
switch (mmu_idx) {
case ARMMMUIdx_Stage2:
case ARMMMUIdx_Stage2_S:
- case ARMMMUIdx_Phys_NS:
case ARMMMUIdx_Phys_S:
+ case ARMMMUIdx_Phys_NS:
+ case ARMMMUIdx_Phys_Root:
+ case ARMMMUIdx_Phys_Realm:
break;
default:
@@ -2830,6 +2834,8 @@ static bool get_phys_addr_with_struct(CPUARMState *env,
S1Translate *ptw,
switch (mmu_idx) {
case ARMMMUIdx_Phys_S:
case ARMMMUIdx_Phys_NS:
+ case ARMMMUIdx_Phys_Root:
+ case ARMMMUIdx_Phys_Realm:
/* Checking Phys early avoids special casing later vs regime_el. */
return get_phys_addr_disabled(env, address, access_type, mmu_idx,
is_secure, result, fi);
--
2.34.1
- [PATCH v2 00/21] target/arm: Implement FEAT_RME, Richard Henderson, 2023/02/20
- [PATCH v2 01/21] target/arm: Rewrite check_s2_mmu_setup, Richard Henderson, 2023/02/20
- [PATCH v2 02/21] target/arm: Add isar_feature_aa64_rme, Richard Henderson, 2023/02/20
- [PATCH v2 03/21] target/arm: Update SCR and HCR for RME, Richard Henderson, 2023/02/20
- [PATCH v2 04/21] target/arm: SCR_EL3.NS may be RES1, Richard Henderson, 2023/02/20
- [PATCH v2 05/21] target/arm: Add RME cpregs, Richard Henderson, 2023/02/20
- [PATCH v2 06/21] target/arm: Introduce ARMSecuritySpace, Richard Henderson, 2023/02/20
- [PATCH v2 07/21] include/exec/memattrs: Add two bits of space to MemTxAttrs, Richard Henderson, 2023/02/20
- [PATCH v2 08/21] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx, Richard Henderson, 2023/02/20
- [PATCH v2 09/21] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root},
Richard Henderson <=
- [PATCH v2 10/21] target/arm: Pipe ARMSecuritySpace through ptw.c, Richard Henderson, 2023/02/20
- [PATCH v2 11/21] target/arm: NSTable is RES0 for the RME EL3 regime, Richard Henderson, 2023/02/20
- [PATCH v2 12/21] target/arm: Handle Block and Page bits for security space, Richard Henderson, 2023/02/20
- [PATCH v2 13/21] target/arm: Handle no-execute for Realm and Root regimes, Richard Henderson, 2023/02/20
- [PATCH v2 14/21] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate, Richard Henderson, 2023/02/20
- [PATCH v2 15/21] target/arm: Move s1_is_el0 into S1Translate, Richard Henderson, 2023/02/20
- [PATCH v2 19/21] target/arm: Implement the granule protection check, Richard Henderson, 2023/02/20
- [PATCH v2 18/21] target/arm: Implement GPC exceptions, Richard Henderson, 2023/02/20
- [PATCH v2 16/21] target/arm: Use get_phys_addr_with_struct for stage2, Richard Henderson, 2023/02/20
- [NOTFORMERGE PATCH v2 20/21] target/arm: Enable RME for -cpu max, Richard Henderson, 2023/02/20