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[PATCH v2 08/21] target/arm: Adjust the order of Phys and Stage2 ARMMMUI
From: |
Richard Henderson |
Subject: |
[PATCH v2 08/21] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx |
Date: |
Mon, 20 Feb 2023 13:26:13 -1000 |
It will be helpful to have ARMMMUIdx_Phys_* to be in the same
relative order as ARMSecuritySpace enumerators. This requires
the adjustment to the nstable check. While there, check for being
in secure state rather than rely on clearing the low bit making
no change to non-secure state.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 12 ++++++------
target/arm/ptw.c | 12 +++++-------
2 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 1b982dc94c..c9585390d4 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2854,18 +2854,18 @@ typedef enum ARMMMUIdx {
ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A,
ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A,
- /* TLBs with 1-1 mapping to the physical address spaces. */
- ARMMMUIdx_Phys_NS = 8 | ARM_MMU_IDX_A,
- ARMMMUIdx_Phys_S = 9 | ARM_MMU_IDX_A,
-
/*
* Used for second stage of an S12 page table walk, or for descriptor
* loads during first stage of an S1 page table walk. Note that both
* are in use simultaneously for SecureEL2: the security state for
* the S2 ptw is selected by the NS bit from the S1 ptw.
*/
- ARMMMUIdx_Stage2 = 10 | ARM_MMU_IDX_A,
- ARMMMUIdx_Stage2_S = 11 | ARM_MMU_IDX_A,
+ ARMMMUIdx_Stage2_S = 8 | ARM_MMU_IDX_A,
+ ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A,
+
+ /* TLBs with 1-1 mapping to the physical address spaces. */
+ ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A,
+ ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A,
/*
* These are not allocated TLBs and are used only for AT system
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 6fb72fb086..5ed5bb5039 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1410,16 +1410,14 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
descaddr |= (address >> (stride * (4 - level))) & indexmask;
descaddr &= ~7ULL;
nstable = extract32(tableattrs, 4, 1);
- if (nstable) {
+ if (nstable && ptw->in_secure) {
/*
* Stage2_S -> Stage2 or Phys_S -> Phys_NS
- * Assert that the non-secure idx are even, and relative order.
+ * Assert the relative order of the secure/non-secure indexes.
*/
- QEMU_BUILD_BUG_ON((ARMMMUIdx_Phys_NS & 1) != 0);
- QEMU_BUILD_BUG_ON((ARMMMUIdx_Stage2 & 1) != 0);
- QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS + 1 != ARMMMUIdx_Phys_S);
- QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2 + 1 != ARMMMUIdx_Stage2_S);
- ptw->in_ptw_idx &= ~1;
+ QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_S + 1 != ARMMMUIdx_Phys_NS);
+ QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2_S + 1 != ARMMMUIdx_Stage2);
+ ptw->in_ptw_idx += 1;
ptw->in_secure = false;
}
if (!S1_ptw_translate(env, ptw, descaddr, fi)) {
--
2.34.1
- [PATCH v2 03/21] target/arm: Update SCR and HCR for RME, (continued)
- [PATCH v2 03/21] target/arm: Update SCR and HCR for RME, Richard Henderson, 2023/02/20
- [PATCH v2 04/21] target/arm: SCR_EL3.NS may be RES1, Richard Henderson, 2023/02/20
- [PATCH v2 05/21] target/arm: Add RME cpregs, Richard Henderson, 2023/02/20
- [PATCH v2 06/21] target/arm: Introduce ARMSecuritySpace, Richard Henderson, 2023/02/20
- [PATCH v2 07/21] include/exec/memattrs: Add two bits of space to MemTxAttrs, Richard Henderson, 2023/02/20
[PATCH v2 08/21] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx,
Richard Henderson <=
[PATCH v2 09/21] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root}, Richard Henderson, 2023/02/20
[PATCH v2 10/21] target/arm: Pipe ARMSecuritySpace through ptw.c, Richard Henderson, 2023/02/20
[PATCH v2 11/21] target/arm: NSTable is RES0 for the RME EL3 regime, Richard Henderson, 2023/02/20
[PATCH v2 12/21] target/arm: Handle Block and Page bits for security space, Richard Henderson, 2023/02/20
[PATCH v2 13/21] target/arm: Handle no-execute for Realm and Root regimes, Richard Henderson, 2023/02/20
[PATCH v2 14/21] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate, Richard Henderson, 2023/02/20
[PATCH v2 15/21] target/arm: Move s1_is_el0 into S1Translate, Richard Henderson, 2023/02/20
[PATCH v2 19/21] target/arm: Implement the granule protection check, Richard Henderson, 2023/02/20
[PATCH v2 18/21] target/arm: Implement GPC exceptions, Richard Henderson, 2023/02/20
[PATCH v2 16/21] target/arm: Use get_phys_addr_with_struct for stage2, Richard Henderson, 2023/02/20