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[PATCH v2 15/21] target/arm: Move s1_is_el0 into S1Translate
From: |
Richard Henderson |
Subject: |
[PATCH v2 15/21] target/arm: Move s1_is_el0 into S1Translate |
Date: |
Mon, 20 Feb 2023 13:26:20 -1000 |
Instead of passing this to get_phys_addr_lpae, stash it
in the S1Translate structure.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/ptw.c | 26 ++++++++++++--------------
1 file changed, 12 insertions(+), 14 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 6e980654be..d4027ce763 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -22,6 +22,12 @@ typedef struct S1Translate {
ARMSecuritySpace in_space;
bool in_secure;
bool in_debug;
+ /*
+ * If this is stage 2 of a stage 1+2 page table walk, then this must
+ * be true if stage 1 is an EL0 access; otherwise this is ignored.
+ * Stage 2 is indicated by in_mmu_idx set to ARMMMUIdx_Stage2{,_S}.
+ */
+ bool in_s1_is_el0;
bool out_secure;
bool out_rw;
bool out_be;
@@ -33,7 +39,7 @@ typedef struct S1Translate {
static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
uint64_t address,
- MMUAccessType access_type, bool s1_is_el0,
+ MMUAccessType access_type,
GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
__attribute__((nonnull));
@@ -1257,17 +1263,12 @@ static int check_s2_mmu_setup(ARMCPU *cpu, bool
is_aa64, uint64_t tcr,
* @ptw: Current and next stage parameters for the walk.
* @address: virtual address to get physical address for
* @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
- * @s1_is_el0: if @ptw->in_mmu_idx is ARMMMUIdx_Stage2
- * (so this is a stage 2 page table walk),
- * must be true if this is stage 2 of a stage 1+2
- * walk for an EL0 access. If @mmu_idx is anything else,
- * @s1_is_el0 is ignored.
* @result: set on translation success,
* @fi: set to fault info if the translation fails
*/
static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
uint64_t address,
- MMUAccessType access_type, bool s1_is_el0,
+ MMUAccessType access_type,
GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
{
ARMCPU *cpu = env_archcpu(env);
@@ -1600,7 +1601,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
result->f.prot = get_S2prot_noexecute(ap);
} else {
xn = extract64(attrs, 53, 2);
- result->f.prot = get_S2prot(env, ap, xn, s1_is_el0);
+ result->f.prot = get_S2prot(env, ap, xn, ptw->in_s1_is_el0);
}
} else {
int nse, ns = extract32(attrs, 5, 1);
@@ -2822,7 +2823,6 @@ static bool get_phys_addr_twostage(CPUARMState *env,
S1Translate *ptw,
bool ret, ipa_secure, s2walk_secure;
ARMCacheAttrs cacheattrs1;
ARMSecuritySpace ipa_space, s2walk_space;
- bool is_el0;
uint64_t hcr;
ret = get_phys_addr_with_struct(env, ptw, address, access_type, result,
fi);
@@ -2847,7 +2847,7 @@ static bool get_phys_addr_twostage(CPUARMState *env,
S1Translate *ptw,
s2walk_space = ipa_space;
}
- is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0;
+ ptw->in_s1_is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0;
ptw->in_mmu_idx = s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
ptw->in_ptw_idx = arm_space_to_phys(s2walk_space);
ptw->in_secure = s2walk_secure;
@@ -2866,8 +2866,7 @@ static bool get_phys_addr_twostage(CPUARMState *env,
S1Translate *ptw,
ret = get_phys_addr_pmsav8(env, ipa, access_type,
ptw->in_mmu_idx, is_secure, result, fi);
} else {
- ret = get_phys_addr_lpae(env, ptw, ipa, access_type,
- is_el0, result, fi);
+ ret = get_phys_addr_lpae(env, ptw, ipa, access_type, result, fi);
}
fi->s2addr = ipa;
@@ -3043,8 +3042,7 @@ static bool get_phys_addr_with_struct(CPUARMState *env,
S1Translate *ptw,
}
if (regime_using_lpae_format(env, mmu_idx)) {
- return get_phys_addr_lpae(env, ptw, address, access_type, false,
- result, fi);
+ return get_phys_addr_lpae(env, ptw, address, access_type, result, fi);
} else if (arm_feature(env, ARM_FEATURE_V7) ||
regime_sctlr(env, mmu_idx) & SCTLR_XP) {
return get_phys_addr_v6(env, ptw, address, access_type, result, fi);
--
2.34.1
- [PATCH v2 07/21] include/exec/memattrs: Add two bits of space to MemTxAttrs, (continued)
- [PATCH v2 07/21] include/exec/memattrs: Add two bits of space to MemTxAttrs, Richard Henderson, 2023/02/20
- [PATCH v2 08/21] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx, Richard Henderson, 2023/02/20
- [PATCH v2 09/21] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root}, Richard Henderson, 2023/02/20
- [PATCH v2 10/21] target/arm: Pipe ARMSecuritySpace through ptw.c, Richard Henderson, 2023/02/20
- [PATCH v2 11/21] target/arm: NSTable is RES0 for the RME EL3 regime, Richard Henderson, 2023/02/20
- [PATCH v2 12/21] target/arm: Handle Block and Page bits for security space, Richard Henderson, 2023/02/20
- [PATCH v2 13/21] target/arm: Handle no-execute for Realm and Root regimes, Richard Henderson, 2023/02/20
- [PATCH v2 14/21] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate, Richard Henderson, 2023/02/20
- [PATCH v2 15/21] target/arm: Move s1_is_el0 into S1Translate,
Richard Henderson <=
- [PATCH v2 19/21] target/arm: Implement the granule protection check, Richard Henderson, 2023/02/20
- [PATCH v2 18/21] target/arm: Implement GPC exceptions, Richard Henderson, 2023/02/20
- [PATCH v2 16/21] target/arm: Use get_phys_addr_with_struct for stage2, Richard Henderson, 2023/02/20
- [NOTFORMERGE PATCH v2 20/21] target/arm: Enable RME for -cpu max, Richard Henderson, 2023/02/20
- [PATCH v2 17/21] target/arm: Add GPC syndrome, Richard Henderson, 2023/02/20
- [NOTFORMERGE PATCH v2 21/21] hw/arm/virt: Add some memory for Realm Management Monitor, Richard Henderson, 2023/02/20