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[PATCH v2 04/21] target/arm: SCR_EL3.NS may be RES1
From: |
Richard Henderson |
Subject: |
[PATCH v2 04/21] target/arm: SCR_EL3.NS may be RES1 |
Date: |
Mon, 20 Feb 2023 13:26:09 -1000 |
With RME, SEL2 must also be present to support secure state.
The NS bit is RES1 if SEL2 is not present.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 42d94e0904..2ebca3e2b6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1856,6 +1856,9 @@ static void scr_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
}
if (cpu_isar_feature(aa64_sel2, cpu)) {
valid_mask |= SCR_EEL2;
+ } else if (cpu_isar_feature(aa64_rme, cpu)) {
+ /* With RME and without SEL2, NS is RES1 (R_GSWWH, I_DJJQJ). */
+ value |= SCR_NS;
}
if (cpu_isar_feature(aa64_mte, cpu)) {
valid_mask |= SCR_ATA;
--
2.34.1
- [PATCH v2 00/21] target/arm: Implement FEAT_RME, Richard Henderson, 2023/02/20
- [PATCH v2 01/21] target/arm: Rewrite check_s2_mmu_setup, Richard Henderson, 2023/02/20
- [PATCH v2 02/21] target/arm: Add isar_feature_aa64_rme, Richard Henderson, 2023/02/20
- [PATCH v2 03/21] target/arm: Update SCR and HCR for RME, Richard Henderson, 2023/02/20
- [PATCH v2 04/21] target/arm: SCR_EL3.NS may be RES1,
Richard Henderson <=
- [PATCH v2 05/21] target/arm: Add RME cpregs, Richard Henderson, 2023/02/20
- [PATCH v2 06/21] target/arm: Introduce ARMSecuritySpace, Richard Henderson, 2023/02/20
- [PATCH v2 07/21] include/exec/memattrs: Add two bits of space to MemTxAttrs, Richard Henderson, 2023/02/20
[PATCH v2 08/21] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx, Richard Henderson, 2023/02/20
[PATCH v2 09/21] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root}, Richard Henderson, 2023/02/20