Re: [Patch 06/14] target/riscv: Add propertie check for Zvfh{min} extens

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Re: [Patch 06/14] target/riscv: Add propertie check for Zvfh{min} extens

From:	Daniel Henrique Barboza
Subject:	Re: [Patch 06/14] target/riscv: Add propertie check for Zvfh{min} extensions
Date:	Tue, 14 Feb 2023 10:23:57 -0300
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1



On 2/14/23 05:38, Weiwei Li wrote:

Add check for Zvfh and Zvfhmin


Nit: Missing period in the end.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---


Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

  target/riscv/cpu.c | 14 ++++++++++++++
  1 file changed, 14 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4797ef9c42..8fe76707a0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -768,6 +768,20 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
*cpu, Error **errp)
          return;
      }

+ if (cpu->cfg.ext_zvfh) {

+        cpu->cfg.ext_zvfhmin = true;
+    }
+
+    if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
+        error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) {
+        error_setg(errp, "Zvfh extensions requires Zfhmin extension");
+        return;
+    }
+
      /* Set the ISA extensions, checks should have happened above */
      if (cpu->cfg.ext_zhinx) {
          cpu->cfg.ext_zhinxmin = true;

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Re: [Patch 05/14] target/riscv: Fix relationship between V, Zve*, F and D, (continued)
- [Patch 07/14] target/riscv: Indent fixes in cpu.c, Weiwei Li, 2023/02/14
  - Re: [Patch 07/14] target/riscv: Indent fixes in cpu.c, Daniel Henrique Barboza, 2023/02/14
- [Patch 03/14] target/riscv: Simplify the check for Zfhmin and Zhinxmin, Weiwei Li, 2023/02/14
  - Re: [Patch 03/14] target/riscv: Simplify the check for Zfhmin and Zhinxmin, Daniel Henrique Barboza, 2023/02/14
- [Patch 01/14] target/riscv: Fix the relationship between Zfhmin and Zfh, Weiwei Li, 2023/02/14
  - Re: [Patch 01/14] target/riscv: Fix the relationship between Zfhmin and Zfh, Daniel Henrique Barboza, 2023/02/14
- [Patch 08/14] target/riscv: Simplify check for Zve32f and Zve64f, Weiwei Li, 2023/02/14
  - Re: [Patch 08/14] target/riscv: Simplify check for Zve32f and Zve64f, Daniel Henrique Barboza, 2023/02/14
- [Patch 06/14] target/riscv: Add propertie check for Zvfh{min} extensions, Weiwei Li, 2023/02/14
  - Re: [Patch 06/14] target/riscv: Add propertie check for Zvfh{min} extensions, Daniel Henrique Barboza <=
- [Patch 04/14] target/riscv: Add cfg properties for Zv* extension, Weiwei Li, 2023/02/14
  - Re: [Patch 04/14] target/riscv: Add cfg properties for Zv* extension, Daniel Henrique Barboza, 2023/02/14
- [Patch 10/14] target/riscv: Remove rebundunt check for zve32f and zve64f, Weiwei Li, 2023/02/14
  - Re: [Patch 10/14] target/riscv: Remove rebundunt check for zve32f and zve64f, Daniel Henrique Barboza, 2023/02/14
- [Patch 11/14] target/riscv: Add support for Zvfh/zvfhmin extensions, Weiwei Li, 2023/02/14
  - Re: [Patch 11/14] target/riscv: Add support for Zvfh/zvfhmin extensions, Daniel Henrique Barboza, 2023/02/14
- [Patch 12/14] target/riscv: Fix check for vectore load/store instructions when EEW=64, Weiwei Li, 2023/02/14
  - Re: [Patch 12/14] target/riscv: Fix check for vectore load/store instructions when EEW=64, Daniel Henrique Barboza, 2023/02/14
- [Patch 13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc, Weiwei Li, 2023/02/14
  - Re: [Patch 13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc, Daniel Henrique Barboza, 2023/02/14

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