Re: [Patch 11/14] target/riscv: Add support for Zvfh/zvfhmin extensions

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Re: [Patch 11/14] target/riscv: Add support for Zvfh/zvfhmin extensions

From:	Daniel Henrique Barboza
Subject:	Re: [Patch 11/14] target/riscv: Add support for Zvfh/zvfhmin extensions
Date:	Tue, 14 Feb 2023 10:30:00 -0300
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1



On 2/14/23 05:38, Weiwei Li wrote:

Zvfh supports vector float point instuctions with SEW = 16


s/instuctions/instructions

and supports conversions between 8-bit integers adn binary16 values


s/adn/and


Zvfhmin supports vfwcvt.f.f.v and vfncvt.f.f.w instructions

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---



Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

  target/riscv/insn_trans/trans_rvv.c.inc | 31 +++++++++++++++++++++++--
  1 file changed, 29 insertions(+), 2 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index 9053759546..9b2c5c9ac0 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -40,6 +40,7 @@ static bool require_rvf(DisasContext *s)

switch (s->sew) {

      case MO_16:
+        return s->cfg_ptr->ext_zvfh;
      case MO_32:
          return s->cfg_ptr->ext_zve32f;
      case MO_64:
@@ -57,6 +58,25 @@ static bool require_scale_rvf(DisasContext *s)

switch (s->sew) {

      case MO_8:
+        return s->cfg_ptr->ext_zvfh;
+    case MO_16:
+        return s->cfg_ptr->ext_zve32f;
+    case MO_32:
+        return s->cfg_ptr->ext_zve64d;
+    default:
+        return false;
+    }
+}
+
+static bool require_scale_rvfmin(DisasContext *s)
+{
+    if (s->mstatus_fs == 0) {
+        return false;
+    }
+
+    switch (s->sew) {
+    case MO_8:
+        return s->cfg_ptr->ext_zvfhmin;
      case MO_16:
          return s->cfg_ptr->ext_zve32f;
      case MO_32:
@@ -2798,7 +2818,7 @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
  static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
  {
      return opfv_widen_check(s, a) &&
-           require_scale_rvf(s) &&
+           require_scale_rvfmin(s) &&
             (s->sew != MO_8);
  }

@@ -2909,6 +2929,13 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)

static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)

+{
+    return opfv_narrow_check(s, a) &&
+           require_scale_rvfmin(s) &&
+           (s->sew != MO_8);
+}
+
+static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
  {
      return opfv_narrow_check(s, a) &&
             require_scale_rvf(s) &&
@@ -2952,7 +2979,7 @@ GEN_OPFV_NARROW_TRANS(vfncvt_f_x_w, opfxv_narrow_check, 
vfncvt_f_x_w,
  GEN_OPFV_NARROW_TRANS(vfncvt_f_f_w, opffv_narrow_check, vfncvt_f_f_w,
                        RISCV_FRM_DYN)
  /* Reuse the helper function from vfncvt.f.f.w */
-GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, opffv_narrow_check, vfncvt_f_f_w,
+GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, opffv_rod_narrow_check, vfncvt_f_f_w,
                        RISCV_FRM_ROD)

static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)

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Re: [Patch 01/14] target/riscv: Fix the relationship between Zfhmin and Zfh, (continued)
- [Patch 08/14] target/riscv: Simplify check for Zve32f and Zve64f, Weiwei Li, 2023/02/14
  - Re: [Patch 08/14] target/riscv: Simplify check for Zve32f and Zve64f, Daniel Henrique Barboza, 2023/02/14
- [Patch 06/14] target/riscv: Add propertie check for Zvfh{min} extensions, Weiwei Li, 2023/02/14
  - Re: [Patch 06/14] target/riscv: Add propertie check for Zvfh{min} extensions, Daniel Henrique Barboza, 2023/02/14
- [Patch 04/14] target/riscv: Add cfg properties for Zv* extension, Weiwei Li, 2023/02/14
  - Re: [Patch 04/14] target/riscv: Add cfg properties for Zv* extension, Daniel Henrique Barboza, 2023/02/14
- [Patch 10/14] target/riscv: Remove rebundunt check for zve32f and zve64f, Weiwei Li, 2023/02/14
  - Re: [Patch 10/14] target/riscv: Remove rebundunt check for zve32f and zve64f, Daniel Henrique Barboza, 2023/02/14
- [Patch 11/14] target/riscv: Add support for Zvfh/zvfhmin extensions, Weiwei Li, 2023/02/14
  - Re: [Patch 11/14] target/riscv: Add support for Zvfh/zvfhmin extensions, Daniel Henrique Barboza <=
- [Patch 12/14] target/riscv: Fix check for vectore load/store instructions when EEW=64, Weiwei Li, 2023/02/14
  - Re: [Patch 12/14] target/riscv: Fix check for vectore load/store instructions when EEW=64, Daniel Henrique Barboza, 2023/02/14
- [Patch 13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc, Weiwei Li, 2023/02/14
  - Re: [Patch 13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc, Daniel Henrique Barboza, 2023/02/14
    - Re: [Patch 13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc, weiwei, 2023/02/14
- [Patch 09/14] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc, Weiwei Li, 2023/02/14
  - Re: [Patch 09/14] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc, Daniel Henrique Barboza, 2023/02/14
- [Patch 14/14] target/riscv: Expose properties for Zv* extension, Weiwei Li, 2023/02/14
  - Re: [Patch 14/14] target/riscv: Expose properties for Zv* extension, Daniel Henrique Barboza, 2023/02/14

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