Re: [Patch 03/14] target/riscv: Simplify the check for Zfhmin and Zhinxm

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Re: [Patch 03/14] target/riscv: Simplify the check for Zfhmin and Zhinxm

From:	Daniel Henrique Barboza
Subject:	Re: [Patch 03/14] target/riscv: Simplify the check for Zfhmin and Zhinxmin
Date:	Tue, 14 Feb 2023 09:12:58 -0300
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1



On 2/14/23 05:38, Weiwei Li wrote:

We needn't check Zfh and Zhinx in these instructions


Nit: missing period in the end.


Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---


Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

  target/riscv/insn_trans/trans_rvzfh.c.inc | 25 +++++++++++------------
  1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc 
b/target/riscv/insn_trans/trans_rvzfh.c.inc
index 2ad5716312..85fc1aa822 100644
--- a/target/riscv/insn_trans/trans_rvzfh.c.inc
+++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
@@ -28,15 +28,14 @@
      }                                  \
  } while (0)

-#define REQUIRE_ZFH_OR_ZFHMIN(ctx) do { \

-    if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin)) { \
+#define REQUIRE_ZFHMIN(ctx) do {              \
+    if (!ctx->cfg_ptr->ext_zfhmin) {          \
          return false;                         \
      }                                         \
  } while (0)

-#define REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx) do { \

-    if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin ||          \
-          ctx->cfg_ptr->ext_zhinx || ctx->cfg_ptr->ext_zhinxmin)) {     \
+#define REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx) do {                 \
+    if (!(ctx->cfg_ptr->ext_zfhmin || ctx->cfg_ptr->ext_zhinxmin)) { \
          return false;                                        \
      }                                                        \
  } while (0)
@@ -47,7 +46,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a)
      TCGv t0;

REQUIRE_FPU;

-    REQUIRE_ZFH_OR_ZFHMIN(ctx);
+    REQUIRE_ZFHMIN(ctx);

decode_save_opc(ctx);

      t0 = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -70,7 +69,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a)
      TCGv t0;

REQUIRE_FPU;

-    REQUIRE_ZFH_OR_ZFHMIN(ctx);
+    REQUIRE_ZFHMIN(ctx);

decode_save_opc(ctx);

      t0 = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -401,7 +400,7 @@ static bool trans_fmax_h(DisasContext *ctx, arg_fmax_h *a)
  static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h *a)
  {
      REQUIRE_FPU;
-    REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
+    REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);

TCGv_i64 dest = dest_fpr(ctx, a->rd);

      TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
@@ -418,7 +417,7 @@ static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h 
*a)
  static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a)
  {
      REQUIRE_FPU;
-    REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
+    REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);
      REQUIRE_ZDINX_OR_D(ctx);

TCGv_i64 dest = dest_fpr(ctx, a->rd);

@@ -436,7 +435,7 @@ static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h 
*a)
  static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s *a)
  {
      REQUIRE_FPU;
-    REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
+    REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);

TCGv_i64 dest = dest_fpr(ctx, a->rd);

      TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
@@ -452,7 +451,7 @@ static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s 
*a)
  static bool trans_fcvt_h_d(DisasContext *ctx, arg_fcvt_h_d *a)
  {
      REQUIRE_FPU;
-    REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
+    REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);
      REQUIRE_ZDINX_OR_D(ctx);

TCGv_i64 dest = dest_fpr(ctx, a->rd);

@@ -585,7 +584,7 @@ static bool trans_fcvt_h_wu(DisasContext *ctx, 
arg_fcvt_h_wu *a)
  static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a)
  {
      REQUIRE_FPU;
-    REQUIRE_ZFH_OR_ZFHMIN(ctx);
+    REQUIRE_ZFHMIN(ctx);

TCGv dest = dest_gpr(ctx, a->rd);@@ -605,7 +604,7 @@ static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a)

  static bool trans_fmv_h_x(DisasContext *ctx, arg_fmv_h_x *a)
  {
      REQUIRE_FPU;
-    REQUIRE_ZFH_OR_ZFHMIN(ctx);
+    REQUIRE_ZFHMIN(ctx);

TCGv t0 = get_gpr(ctx, a->rs1, EXT_ZERO);

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[Patch 00/14] target/riscv: Some updates to float point related extensions, Weiwei Li, 2023/02/14
- [Patch 02/14] target/riscv: Fix the relationship between Zhinxmin and Zhinx, Weiwei Li, 2023/02/14
  - Re: [Patch 02/14] target/riscv: Fix the relationship between Zhinxmin and Zhinx, Daniel Henrique Barboza, 2023/02/14
- [Patch 05/14] target/riscv: Fix relationship between V, Zve*, F and D, Weiwei Li, 2023/02/14
  - Re: [Patch 05/14] target/riscv: Fix relationship between V, Zve*, F and D, Daniel Henrique Barboza, 2023/02/14
- [Patch 07/14] target/riscv: Indent fixes in cpu.c, Weiwei Li, 2023/02/14
  - Re: [Patch 07/14] target/riscv: Indent fixes in cpu.c, Daniel Henrique Barboza, 2023/02/14
- [Patch 03/14] target/riscv: Simplify the check for Zfhmin and Zhinxmin, Weiwei Li, 2023/02/14
  - Re: [Patch 03/14] target/riscv: Simplify the check for Zfhmin and Zhinxmin, Daniel Henrique Barboza <=
- [Patch 01/14] target/riscv: Fix the relationship between Zfhmin and Zfh, Weiwei Li, 2023/02/14
  - Re: [Patch 01/14] target/riscv: Fix the relationship between Zfhmin and Zfh, Daniel Henrique Barboza, 2023/02/14
- [Patch 08/14] target/riscv: Simplify check for Zve32f and Zve64f, Weiwei Li, 2023/02/14
  - Re: [Patch 08/14] target/riscv: Simplify check for Zve32f and Zve64f, Daniel Henrique Barboza, 2023/02/14
- [Patch 06/14] target/riscv: Add propertie check for Zvfh{min} extensions, Weiwei Li, 2023/02/14
  - Re: [Patch 06/14] target/riscv: Add propertie check for Zvfh{min} extensions, Daniel Henrique Barboza, 2023/02/14
- [Patch 04/14] target/riscv: Add cfg properties for Zv* extension, Weiwei Li, 2023/02/14
  - Re: [Patch 04/14] target/riscv: Add cfg properties for Zv* extension, Daniel Henrique Barboza, 2023/02/14
- [Patch 10/14] target/riscv: Remove rebundunt check for zve32f and zve64f, Weiwei Li, 2023/02/14
  - Re: [Patch 10/14] target/riscv: Remove rebundunt check for zve32f and zve64f, Daniel Henrique Barboza, 2023/02/14

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