Re: [Patch 08/14] target/riscv: Simplify check for Zve32f and Zve64f

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Re: [Patch 08/14] target/riscv: Simplify check for Zve32f and Zve64f

From:	Daniel Henrique Barboza
Subject:	Re: [Patch 08/14] target/riscv: Simplify check for Zve32f and Zve64f
Date:	Tue, 14 Feb 2023 10:25:20 -0300
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1



On 2/14/23 05:38, Weiwei Li wrote:

Zve64f depends on Zve32f, so we can only check Zve32f
in these cases

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---



Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

  target/riscv/insn_trans/trans_rvv.c.inc | 8 ++------
  1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index bbb5c3a7b5..6f7ecf1a68 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -173,9 +173,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, 
TCGv s2)
  {
      TCGv s1, dst;

- if (!require_rvv(s) ||

-        !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f ||
-          s->cfg_ptr->ext_zve64f)) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
          return false;
      }

@@ -210,9 +208,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)

  {
      TCGv dst;

- if (!require_rvv(s) ||

-        !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f ||
-          s->cfg_ptr->ext_zve64f)) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
          return false;
      }

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[Patch 05/14] target/riscv: Fix relationship between V, Zve*, F and D, (continued)
- [Patch 05/14] target/riscv: Fix relationship between V, Zve*, F and D, Weiwei Li, 2023/02/14
  - Re: [Patch 05/14] target/riscv: Fix relationship between V, Zve*, F and D, Daniel Henrique Barboza, 2023/02/14
    - Re: [Patch 05/14] target/riscv: Fix relationship between V, Zve*, F and D, weiwei, 2023/02/14
- [Patch 07/14] target/riscv: Indent fixes in cpu.c, Weiwei Li, 2023/02/14
  - Re: [Patch 07/14] target/riscv: Indent fixes in cpu.c, Daniel Henrique Barboza, 2023/02/14
- [Patch 03/14] target/riscv: Simplify the check for Zfhmin and Zhinxmin, Weiwei Li, 2023/02/14
  - Re: [Patch 03/14] target/riscv: Simplify the check for Zfhmin and Zhinxmin, Daniel Henrique Barboza, 2023/02/14
- [Patch 01/14] target/riscv: Fix the relationship between Zfhmin and Zfh, Weiwei Li, 2023/02/14
  - Re: [Patch 01/14] target/riscv: Fix the relationship between Zfhmin and Zfh, Daniel Henrique Barboza, 2023/02/14
- [Patch 08/14] target/riscv: Simplify check for Zve32f and Zve64f, Weiwei Li, 2023/02/14
  - Re: [Patch 08/14] target/riscv: Simplify check for Zve32f and Zve64f, Daniel Henrique Barboza <=
- [Patch 06/14] target/riscv: Add propertie check for Zvfh{min} extensions, Weiwei Li, 2023/02/14
  - Re: [Patch 06/14] target/riscv: Add propertie check for Zvfh{min} extensions, Daniel Henrique Barboza, 2023/02/14
- [Patch 04/14] target/riscv: Add cfg properties for Zv* extension, Weiwei Li, 2023/02/14
  - Re: [Patch 04/14] target/riscv: Add cfg properties for Zv* extension, Daniel Henrique Barboza, 2023/02/14
- [Patch 10/14] target/riscv: Remove rebundunt check for zve32f and zve64f, Weiwei Li, 2023/02/14
  - Re: [Patch 10/14] target/riscv: Remove rebundunt check for zve32f and zve64f, Daniel Henrique Barboza, 2023/02/14
- [Patch 11/14] target/riscv: Add support for Zvfh/zvfhmin extensions, Weiwei Li, 2023/02/14
  - Re: [Patch 11/14] target/riscv: Add support for Zvfh/zvfhmin extensions, Daniel Henrique Barboza, 2023/02/14
- [Patch 12/14] target/riscv: Fix check for vectore load/store instructions when EEW=64, Weiwei Li, 2023/02/14
  - Re: [Patch 12/14] target/riscv: Fix check for vectore load/store instructions when EEW=64, Daniel Henrique Barboza, 2023/02/14

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