Re: [Patch 13/14] target/riscv: Simplify check for EEW = 64 in trans

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Re: [Patch 13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv

From:	Daniel Henrique Barboza
Subject:	Re: [Patch 13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc
Date:	Tue, 14 Feb 2023 10:37:20 -0300
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1



On 2/14/23 05:38, Weiwei Li wrote:

Only V extension support EEW = 64 in these case: Zve64* extensions
don't support EEW = 64 as commented


"as commented" where? In the previous patch?


Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---


The code LGTM.

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

  target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++--------
  1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index 5dbdce073b..fc0d0d60e8 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1998,8 +1998,7 @@ static bool vmulh_vv_check(DisasContext *s, arg_rmrr *a)
       * are not included for EEW=64 in Zve64*. (Section 18.2)
       */
      return opivv_check(s, a) &&
-           (!has_ext(s, RVV) &&
-            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
+           (!has_ext(s, RVV) ? s->sew != MO_64 : true);
  }

static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)

@@ -2012,8 +2011,7 @@ static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
       * are not included for EEW=64 in Zve64*. (Section 18.2)
       */
      return opivx_check(s, a) &&
-           (!has_ext(s, RVV) &&
-            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
+           (!has_ext(s, RVV) ? s->sew != MO_64 : true);
  }

GEN_OPIVV_GVEC_TRANS(vmul_vv, mul)

@@ -2230,8 +2228,7 @@ static bool vsmul_vv_check(DisasContext *s, arg_rmrr *a)
       * for EEW=64 in Zve64*. (Section 18.2)
       */
      return opivv_check(s, a) &&
-           (!has_ext(s, RVV) &&
-            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
+           (!has_ext(s, RVV) ? s->sew != MO_64 : true);
  }

static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)

@@ -2242,8 +2239,7 @@ static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
       * for EEW=64 in Zve64*. (Section 18.2)
       */
      return opivx_check(s, a) &&
-           (!has_ext(s, RVV) &&
-            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
+           (!has_ext(s, RVV) ? s->sew != MO_64 : true);
  }

GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check)

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Re: [Patch 06/14] target/riscv: Add propertie check for Zvfh{min} extensions, (continued)
- [Patch 04/14] target/riscv: Add cfg properties for Zv* extension, Weiwei Li, 2023/02/14
  - Re: [Patch 04/14] target/riscv: Add cfg properties for Zv* extension, Daniel Henrique Barboza, 2023/02/14
- [Patch 10/14] target/riscv: Remove rebundunt check for zve32f and zve64f, Weiwei Li, 2023/02/14
  - Re: [Patch 10/14] target/riscv: Remove rebundunt check for zve32f and zve64f, Daniel Henrique Barboza, 2023/02/14
- [Patch 11/14] target/riscv: Add support for Zvfh/zvfhmin extensions, Weiwei Li, 2023/02/14
  - Re: [Patch 11/14] target/riscv: Add support for Zvfh/zvfhmin extensions, Daniel Henrique Barboza, 2023/02/14
- [Patch 12/14] target/riscv: Fix check for vectore load/store instructions when EEW=64, Weiwei Li, 2023/02/14
  - Re: [Patch 12/14] target/riscv: Fix check for vectore load/store instructions when EEW=64, Daniel Henrique Barboza, 2023/02/14
- [Patch 13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc, Weiwei Li, 2023/02/14
  - Re: [Patch 13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc, Daniel Henrique Barboza <=
    - Re: [Patch 13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc, weiwei, 2023/02/14
- [Patch 09/14] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc, Weiwei Li, 2023/02/14
  - Re: [Patch 09/14] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc, Daniel Henrique Barboza, 2023/02/14
- [Patch 14/14] target/riscv: Expose properties for Zv* extension, Weiwei Li, 2023/02/14
  - Re: [Patch 14/14] target/riscv: Expose properties for Zv* extension, Daniel Henrique Barboza, 2023/02/14

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