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[PULL 28/42] target/ppc: Introduce macros to check isa extensions
From: |
David Gibson |
Subject: |
[PULL 28/42] target/ppc: Introduce macros to check isa extensions |
Date: |
Thu, 3 Jun 2021 18:22:17 +1000 |
From: Richard Henderson <richard.henderson@linaro.org>
These will be used by the decodetree trans_* functions
to early-exit when the instruction set is not enabled.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20210601193528.2533031-2-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index e16a2721e2..11fd3342a0 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7664,6 +7664,32 @@ static inline void set_avr64(int regno, TCGv_i64 src,
bool high)
tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
}
+/*
+ * Helpers for trans_* functions to check for specific insns flags.
+ * Use token pasting to ensure that we use the proper flag with the
+ * proper variable.
+ */
+#define REQUIRE_INSNS_FLAGS(CTX, NAME) \
+ do { \
+ if (((CTX)->insns_flags & PPC_##NAME) == 0) { \
+ return false; \
+ } \
+ } while (0)
+
+#define REQUIRE_INSNS_FLAGS2(CTX, NAME) \
+ do { \
+ if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \
+ return false; \
+ } \
+ } while (0)
+
+/* Then special-case the check for 64-bit so that we elide code for ppc32. */
+#if TARGET_LONG_BITS == 32
+# define REQUIRE_64BIT(CTX) return false
+#else
+# define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B)
+#endif
+
#include "translate/fp-impl.c.inc"
#include "translate/vmx-impl.c.inc"
--
2.31.1
- [PULL 24/42] target/ppc: overhauled and moved logic of storing fpscr, (continued)
- [PULL 24/42] target/ppc: overhauled and moved logic of storing fpscr, David Gibson, 2021/06/03
- [PULL 23/42] target/ppc: removed all mentions to PPC_DUMP_CPU, David Gibson, 2021/06/03
- [PULL 22/42] target/ppc: removed GEN_OPCODE decision tree, David Gibson, 2021/06/03
- [PULL 15/42] target/ppc: updated meson.build to support disable-tcg, David Gibson, 2021/06/03
- [PULL 16/42] target/ppc: remove ppc_cpu_dump_statistics, David Gibson, 2021/06/03
- [PULL 31/42] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI, David Gibson, 2021/06/03
- [PULL 19/42] ppc/pef.c: initialize cgs->ready in kvmppc_svm_init(), David Gibson, 2021/06/03
- [PULL 25/42] target/ppc: powerpc_excp: Move lpes code to where it is used, David Gibson, 2021/06/03
- [PULL 32/42] target/ppc: Implement PNOP, David Gibson, 2021/06/03
- [PULL 36/42] target/ppc: Implement prefixed integer store instructions, David Gibson, 2021/06/03
- [PULL 28/42] target/ppc: Introduce macros to check isa extensions,
David Gibson <=
- [PULL 26/42] target/ppc: powerpc_excp: Remove dump_syscall_vectored, David Gibson, 2021/06/03
- [PULL 27/42] target/ppc: powerpc_excp: Consolidade TLB miss code, David Gibson, 2021/06/03
- [PULL 30/42] target/ppc: Add infrastructure for prefixed insns, David Gibson, 2021/06/03
- [PULL 29/42] target/ppc: Move page crossing check to ppc_tr_translate_insn, David Gibson, 2021/06/03
- [PULL 34/42] target/ppc: Implement prefixed integer load instructions, David Gibson, 2021/06/03
- [PULL 33/42] target/ppc: Move D/DS/X-form integer loads to decodetree, David Gibson, 2021/06/03
- [PULL 37/42] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions, David Gibson, 2021/06/03
- [PULL 35/42] target/ppc: Move D/DS/X-form integer stores to decodetree, David Gibson, 2021/06/03
- [PULL 40/42] target/ppc: Move addpcis to decodetree, David Gibson, 2021/06/03
- [PULL 38/42] target/ppc: Implement cfuged instruction, David Gibson, 2021/06/03