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[PULL 27/42] target/ppc: powerpc_excp: Consolidade TLB miss code
From: |
David Gibson |
Subject: |
[PULL 27/42] target/ppc: powerpc_excp: Consolidade TLB miss code |
Date: |
Thu, 3 Jun 2021 18:22:16 +1000 |
From: Fabiano Rosas <farosas@linux.ibm.com>
The only difference in the code for Instruction fetch, Data load and
Data store TLB miss errors is that when called from an unsupported
processor (i.e. not one of 602, 603, 603e, G2, 7x5 or 74xx), they
abort with a message specific to the operation type (insn fetch, data
load/store).
If a processor does not support those interrupts we should not be
registering them in init_excp_<proc> to begin with, so that error
message would never be used.
I'm leaving the message in for completeness, but making it generic and
consolidating the three interrupts into the same case statement body.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20210601214649.785647-4-farosas@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/excp_helper.c | 37 ++-----------------------------------
1 file changed, 2 insertions(+), 35 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 9e3aae1c96..fd147e2a37 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -689,52 +689,20 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
"is not implemented yet !\n");
break;
case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
- switch (excp_model) {
- case POWERPC_EXCP_602:
- case POWERPC_EXCP_603:
- case POWERPC_EXCP_603E:
- case POWERPC_EXCP_G2:
- goto tlb_miss_tgpr;
- case POWERPC_EXCP_7x5:
- goto tlb_miss;
- case POWERPC_EXCP_74xx:
- goto tlb_miss_74xx;
- default:
- cpu_abort(cs, "Invalid instruction TLB miss exception\n");
- break;
- }
- break;
case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
- switch (excp_model) {
- case POWERPC_EXCP_602:
- case POWERPC_EXCP_603:
- case POWERPC_EXCP_603E:
- case POWERPC_EXCP_G2:
- goto tlb_miss_tgpr;
- case POWERPC_EXCP_7x5:
- goto tlb_miss;
- case POWERPC_EXCP_74xx:
- goto tlb_miss_74xx;
- default:
- cpu_abort(cs, "Invalid data load TLB miss exception\n");
- break;
- }
- break;
case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
switch (excp_model) {
case POWERPC_EXCP_602:
case POWERPC_EXCP_603:
case POWERPC_EXCP_603E:
case POWERPC_EXCP_G2:
- tlb_miss_tgpr:
/* Swap temporary saved registers with GPRs */
if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
new_msr |= (target_ulong)1 << MSR_TGPR;
hreg_swap_gpr_tgpr(env);
}
- goto tlb_miss;
+ /* fall through */
case POWERPC_EXCP_7x5:
- tlb_miss:
#if defined(DEBUG_SOFTWARE_TLB)
if (qemu_log_enabled()) {
const char *es;
@@ -769,7 +737,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
break;
case POWERPC_EXCP_74xx:
- tlb_miss_74xx:
#if defined(DEBUG_SOFTWARE_TLB)
if (qemu_log_enabled()) {
const char *es;
@@ -799,7 +766,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
msr |= env->error_code; /* key bit */
break;
default:
- cpu_abort(cs, "Invalid data store TLB miss exception\n");
+ cpu_abort(cs, "Invalid TLB miss exception\n");
break;
}
break;
--
2.31.1
- [PULL 22/42] target/ppc: removed GEN_OPCODE decision tree, (continued)
- [PULL 22/42] target/ppc: removed GEN_OPCODE decision tree, David Gibson, 2021/06/03
- [PULL 15/42] target/ppc: updated meson.build to support disable-tcg, David Gibson, 2021/06/03
- [PULL 16/42] target/ppc: remove ppc_cpu_dump_statistics, David Gibson, 2021/06/03
- [PULL 31/42] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI, David Gibson, 2021/06/03
- [PULL 19/42] ppc/pef.c: initialize cgs->ready in kvmppc_svm_init(), David Gibson, 2021/06/03
- [PULL 25/42] target/ppc: powerpc_excp: Move lpes code to where it is used, David Gibson, 2021/06/03
- [PULL 32/42] target/ppc: Implement PNOP, David Gibson, 2021/06/03
- [PULL 36/42] target/ppc: Implement prefixed integer store instructions, David Gibson, 2021/06/03
- [PULL 28/42] target/ppc: Introduce macros to check isa extensions, David Gibson, 2021/06/03
- [PULL 26/42] target/ppc: powerpc_excp: Remove dump_syscall_vectored, David Gibson, 2021/06/03
- [PULL 27/42] target/ppc: powerpc_excp: Consolidade TLB miss code,
David Gibson <=
- [PULL 30/42] target/ppc: Add infrastructure for prefixed insns, David Gibson, 2021/06/03
- [PULL 29/42] target/ppc: Move page crossing check to ppc_tr_translate_insn, David Gibson, 2021/06/03
- [PULL 34/42] target/ppc: Implement prefixed integer load instructions, David Gibson, 2021/06/03
- [PULL 33/42] target/ppc: Move D/DS/X-form integer loads to decodetree, David Gibson, 2021/06/03
- [PULL 37/42] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions, David Gibson, 2021/06/03
- [PULL 35/42] target/ppc: Move D/DS/X-form integer stores to decodetree, David Gibson, 2021/06/03
- [PULL 40/42] target/ppc: Move addpcis to decodetree, David Gibson, 2021/06/03
- [PULL 38/42] target/ppc: Implement cfuged instruction, David Gibson, 2021/06/03
- [PULL 39/42] target/ppc: Implement vcfuged instruction, David Gibson, 2021/06/03
- [PULL 42/42] target/ppc: fix single-step exception regression, David Gibson, 2021/06/03