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[PULL 25/42] target/ppc: powerpc_excp: Move lpes code to where it is use
From: |
David Gibson |
Subject: |
[PULL 25/42] target/ppc: powerpc_excp: Move lpes code to where it is used |
Date: |
Thu, 3 Jun 2021 18:22:14 +1000 |
From: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20210601214649.785647-2-farosas@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/excp_helper.c | 47 +++++++++++++++++++++-------------------
1 file changed, 25 insertions(+), 22 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 04418054f5..5ea8503b46 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -333,7 +333,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
int srr0, srr1, asrr0, asrr1, lev = -1;
- bool lpes0;
qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
" => %08x (%02x)\n", env->nip, excp, env->error_code);
@@ -365,27 +364,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
excp = powerpc_reset_wakeup(cs, env, excp, &msr);
}
- /*
- * Exception targeting modifiers
- *
- * LPES0 is supported on POWER7/8/9
- * LPES1 is not supported (old iSeries mode)
- *
- * On anything else, we behave as if LPES0 is 1
- * (externals don't alter MSR:HV)
- */
-#if defined(TARGET_PPC64)
- if (excp_model == POWERPC_EXCP_POWER7 ||
- excp_model == POWERPC_EXCP_POWER8 ||
- excp_model == POWERPC_EXCP_POWER9 ||
- excp_model == POWERPC_EXCP_POWER10) {
- lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
- } else
-#endif /* defined(TARGET_PPC64) */
- {
- lpes0 = true;
- }
-
/*
* Hypervisor emulation assistance interrupt only exists on server
* arch 2.05 server or later. We also don't want to generate it if
@@ -473,8 +451,32 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
msr |= env->error_code;
break;
case POWERPC_EXCP_EXTERNAL: /* External input */
+ {
+ bool lpes0;
+
cs = CPU(cpu);
+ /*
+ * Exception targeting modifiers
+ *
+ * LPES0 is supported on POWER7/8/9
+ * LPES1 is not supported (old iSeries mode)
+ *
+ * On anything else, we behave as if LPES0 is 1
+ * (externals don't alter MSR:HV)
+ */
+#if defined(TARGET_PPC64)
+ if (excp_model == POWERPC_EXCP_POWER7 ||
+ excp_model == POWERPC_EXCP_POWER8 ||
+ excp_model == POWERPC_EXCP_POWER9 ||
+ excp_model == POWERPC_EXCP_POWER10) {
+ lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
+ } else
+#endif /* defined(TARGET_PPC64) */
+ {
+ lpes0 = true;
+ }
+
if (!lpes0) {
new_msr |= (target_ulong)MSR_HVB;
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
@@ -486,6 +488,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
}
break;
+ }
case POWERPC_EXCP_ALIGN: /* Alignment exception */
/* Get rS/rD and rA from faulting opcode */
/*
--
2.31.1
- [PULL 21/42] HMP: added info cpustats to removed_features.rst, (continued)
- [PULL 21/42] HMP: added info cpustats to removed_features.rst, David Gibson, 2021/06/03
- [PULL 17/42] target/ppc: removed mentions to DO_PPC_STATISTICS, David Gibson, 2021/06/03
- [PULL 20/42] hw/core/cpu: removed cpu_dump_statistics function, David Gibson, 2021/06/03
- [PULL 24/42] target/ppc: overhauled and moved logic of storing fpscr, David Gibson, 2021/06/03
- [PULL 23/42] target/ppc: removed all mentions to PPC_DUMP_CPU, David Gibson, 2021/06/03
- [PULL 22/42] target/ppc: removed GEN_OPCODE decision tree, David Gibson, 2021/06/03
- [PULL 15/42] target/ppc: updated meson.build to support disable-tcg, David Gibson, 2021/06/03
- [PULL 16/42] target/ppc: remove ppc_cpu_dump_statistics, David Gibson, 2021/06/03
- [PULL 31/42] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI, David Gibson, 2021/06/03
- [PULL 19/42] ppc/pef.c: initialize cgs->ready in kvmppc_svm_init(), David Gibson, 2021/06/03
- [PULL 25/42] target/ppc: powerpc_excp: Move lpes code to where it is used,
David Gibson <=
- [PULL 32/42] target/ppc: Implement PNOP, David Gibson, 2021/06/03
- [PULL 36/42] target/ppc: Implement prefixed integer store instructions, David Gibson, 2021/06/03
- [PULL 28/42] target/ppc: Introduce macros to check isa extensions, David Gibson, 2021/06/03
- [PULL 26/42] target/ppc: powerpc_excp: Remove dump_syscall_vectored, David Gibson, 2021/06/03
- [PULL 27/42] target/ppc: powerpc_excp: Consolidade TLB miss code, David Gibson, 2021/06/03
- [PULL 30/42] target/ppc: Add infrastructure for prefixed insns, David Gibson, 2021/06/03
- [PULL 29/42] target/ppc: Move page crossing check to ppc_tr_translate_insn, David Gibson, 2021/06/03
- [PULL 34/42] target/ppc: Implement prefixed integer load instructions, David Gibson, 2021/06/03
- [PULL 33/42] target/ppc: Move D/DS/X-form integer loads to decodetree, David Gibson, 2021/06/03
- [PULL 37/42] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions, David Gibson, 2021/06/03