[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 05/36] target/mips: Migrate missing CPU fields
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 05/36] target/mips: Migrate missing CPU fields |
Date: |
Sun, 2 May 2021 18:15:07 +0200 |
Add various missing fields to the CPU migration vmstate:
- CP0_VPControl & CP0_GlobalNumber (01bc435b44b 2016-02-03)
- CMGCRBase (c870e3f52ca 2016-03-15)
- CP0_ErrCtl (0d74a222c27 2016-03-25)
- MXU GPR[] & CR (eb5559f67dc 2018-10-18)
- R5900 128-bit upper half (a168a796e1c 2019-01-17)
This is a migration break.
Fixes: 01bc435b44b ("target-mips: implement R6 multi-threading")
Fixes: c870e3f52ca ("target-mips: add CMGCRBase register")
Fixes: 0d74a222c27 ("target-mips: make ITC Configuration Tags accessible to the
CPU")
Fixes: eb5559f67dc ("target/mips: Introduce MXU registers")
Fixes: a168a796e1c ("target/mips: Introduce 32 R5900 multimedia registers")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210423220044.3004195-1-f4bug@amsat.org>
---
target/mips/machine.c | 21 +++++++++++++++------
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/target/mips/machine.c b/target/mips/machine.c
index b5fda6a2786..80d37f9c2fc 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -81,6 +81,9 @@ const VMStateDescription vmstate_inactive_fpu = {
static VMStateField vmstate_tc_fields[] = {
VMSTATE_UINTTL_ARRAY(gpr, TCState, 32),
+#if defined(TARGET_MIPS64)
+ VMSTATE_UINT64_ARRAY(gpr_hi, TCState, 32),
+#endif /* TARGET_MIPS64 */
VMSTATE_UINTTL(PC, TCState),
VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC),
VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC),
@@ -95,20 +98,22 @@ static VMStateField vmstate_tc_fields[] = {
VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
VMSTATE_UINTTL(CP0_UserLocal, TCState),
VMSTATE_INT32(msacsr, TCState),
+ VMSTATE_UINTTL_ARRAY(mxu_gpr, TCState, NUMBER_OF_MXU_REGISTERS - 1),
+ VMSTATE_UINTTL(mxu_cr, TCState),
VMSTATE_END_OF_LIST()
};
const VMStateDescription vmstate_tc = {
.name = "cpu/tc",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = vmstate_tc_fields
};
const VMStateDescription vmstate_inactive_tc = {
.name = "cpu/inactive_tc",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = vmstate_tc_fields
};
@@ -213,8 +218,8 @@ const VMStateDescription vmstate_tlb = {
const VMStateDescription vmstate_mips_cpu = {
.name = "cpu",
- .version_id = 20,
- .minimum_version_id = 20,
+ .version_id = 21,
+ .minimum_version_id = 21,
.post_load = cpu_post_load,
.fields = (VMStateField[]) {
/* Active TC */
@@ -241,6 +246,7 @@ const VMStateDescription vmstate_mips_cpu = {
/* Remaining CP0 registers */
VMSTATE_INT32(env.CP0_Index, MIPSCPU),
+ VMSTATE_INT32(env.CP0_VPControl, MIPSCPU),
VMSTATE_INT32(env.CP0_Random, MIPSCPU),
VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU),
VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU),
@@ -251,6 +257,7 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU),
VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU),
VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU),
+ VMSTATE_INT32(env.CP0_GlobalNumber, MIPSCPU),
VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
VMSTATE_INT32(env.CP0_MemoryMapID, MIPSCPU),
VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
@@ -286,6 +293,7 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU),
VMSTATE_INT32(env.CP0_PRid, MIPSCPU),
VMSTATE_UINTTL(env.CP0_EBase, MIPSCPU),
+ VMSTATE_UINTTL(env.CP0_CMGCRBase, MIPSCPU),
VMSTATE_INT32(env.CP0_Config0, MIPSCPU),
VMSTATE_INT32(env.CP0_Config1, MIPSCPU),
VMSTATE_INT32(env.CP0_Config2, MIPSCPU),
@@ -305,6 +313,7 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_INT32(env.CP0_Debug, MIPSCPU),
VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU),
VMSTATE_INT32(env.CP0_Performance0, MIPSCPU),
+ VMSTATE_INT32(env.CP0_ErrCtl, MIPSCPU),
VMSTATE_UINT64(env.CP0_TagLo, MIPSCPU),
VMSTATE_INT32(env.CP0_DataLo, MIPSCPU),
VMSTATE_INT32(env.CP0_TagHi, MIPSCPU),
--
2.26.3
- [PULL 00/36] MIPS patches for 2021-05-02, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 01/36] hw/isa/piix4: Use qdev_get_gpio_in_named() to get ISA IRQ, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 02/36] target/mips: Fix CACHEE opcode (CACHE using EVA addressing), Philippe Mathieu-Daudé, 2021/05/02
- [PULL 03/36] target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 04/36] target/mips: Remove spurious LOG_UNIMP of MTHC0 opcode, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 05/36] target/mips: Migrate missing CPU fields,
Philippe Mathieu-Daudé <=
- [PULL 06/36] target/mips: Make check_cp0_enabled() return a boolean, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 07/36] target/mips: Simplify meson TCG rules, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 08/36] target/mips: Move IEEE rounding mode array to new source file, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 09/36] target/mips: Move msa_reset() to new source file, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 10/36] target/mips: Make CPU/FPU regnames[] arrays global, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 11/36] target/mips: Optimize CPU/FPU regnames[] arrays, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 12/36] target/mips: Restrict mips_cpu_dump_state() to cpu.c, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 13/36] target/mips: Turn printfpr() macro into a proper function, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 14/36] target/mips: Declare mips_env_set_pc() inlined in "internal.h", Philippe Mathieu-Daudé, 2021/05/02
- [PULL 15/36] target/mips: Merge do_translate_address into cpu_mips_translate_address, Philippe Mathieu-Daudé, 2021/05/02