[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 15/36] target/mips: Merge do_translate_address into cpu_mips_trans
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 15/36] target/mips: Merge do_translate_address into cpu_mips_translate_address |
Date: |
Sun, 2 May 2021 18:15:17 +0200 |
Currently cpu_mips_translate_address() calls raise_mmu_exception(),
and do_translate_address() calls cpu_loop_exit_restore().
This API split is dangerous, we could call cpu_mips_translate_address
without returning to the main loop.
As there is only one caller, it is trivial (and safer) to merge
do_translate_address() back to cpu_mips_translate_address().
Reported-by: Richard Henderson <richard.henderson@linaro.org>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-10-f4bug@amsat.org>
---
target/mips/internal.h | 2 +-
target/mips/op_helper.c | 20 ++------------------
target/mips/tlb_helper.c | 11 ++++++-----
3 files changed, 9 insertions(+), 24 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 04f4b3d6614..e93e057bece 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -148,7 +148,7 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr
physaddr,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
- MMUAccessType access_type);
+ MMUAccessType access_type, uintptr_t
retaddr);
#endif
#define cpu_signal_handler cpu_mips_signal_handler
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 222a0d7c7b3..61e68cc8bed 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -287,23 +287,6 @@ target_ulong helper_rotx(target_ulong rs, uint32_t shift,
uint32_t shiftx,
#ifndef CONFIG_USER_ONLY
-static inline hwaddr do_translate_address(CPUMIPSState *env,
- target_ulong address,
- MMUAccessType access_type,
- uintptr_t retaddr)
-{
- hwaddr paddr;
- CPUState *cs = env_cpu(env);
-
- paddr = cpu_mips_translate_address(env, address, access_type);
-
- if (paddr == -1LL) {
- cpu_loop_exit_restore(cs, retaddr);
- } else {
- return paddr;
- }
-}
-
#define HELPER_LD_ATOMIC(name, insn, almask, do_cast) \
target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
{ \
@@ -313,7 +296,8 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong
arg, int mem_idx) \
} \
do_raise_exception(env, EXCP_AdEL, GETPC()); \
} \
- env->CP0_LLAddr = do_translate_address(env, arg, MMU_DATA_LOAD, GETPC()); \
+ env->CP0_LLAddr = cpu_mips_translate_address(env, arg, MMU_DATA_LOAD, \
+ GETPC()); \
env->lladdr = arg; \
env->llval = do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC()); \
return env->llval; \
diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c
index 8d3ea497803..1ffdc1f8304 100644
--- a/target/mips/tlb_helper.c
+++ b/target/mips/tlb_helper.c
@@ -904,21 +904,22 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
#ifndef CONFIG_USER_ONLY
hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
- MMUAccessType access_type)
+ MMUAccessType access_type, uintptr_t retaddr)
{
hwaddr physical;
int prot;
int ret = 0;
+ CPUState *cs = env_cpu(env);
/* data access */
ret = get_physical_address(env, &physical, &prot, address, access_type,
cpu_mmu_index(env, false));
- if (ret != TLBRET_MATCH) {
- raise_mmu_exception(env, address, access_type, ret);
- return -1LL;
- } else {
+ if (ret == TLBRET_MATCH) {
return physical;
}
+
+ raise_mmu_exception(env, address, access_type, ret);
+ cpu_loop_exit_restore(cs, retaddr);
}
static void set_hflags_for_handler(CPUMIPSState *env)
--
2.26.3
- [PULL 05/36] target/mips: Migrate missing CPU fields, (continued)
- [PULL 05/36] target/mips: Migrate missing CPU fields, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 06/36] target/mips: Make check_cp0_enabled() return a boolean, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 07/36] target/mips: Simplify meson TCG rules, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 08/36] target/mips: Move IEEE rounding mode array to new source file, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 09/36] target/mips: Move msa_reset() to new source file, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 10/36] target/mips: Make CPU/FPU regnames[] arrays global, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 11/36] target/mips: Optimize CPU/FPU regnames[] arrays, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 12/36] target/mips: Restrict mips_cpu_dump_state() to cpu.c, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 13/36] target/mips: Turn printfpr() macro into a proper function, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 14/36] target/mips: Declare mips_env_set_pc() inlined in "internal.h", Philippe Mathieu-Daudé, 2021/05/02
- [PULL 15/36] target/mips: Merge do_translate_address into cpu_mips_translate_address,
Philippe Mathieu-Daudé <=
- [PULL 16/36] target/mips: Extract load/store helpers to ldst_helper.c, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 17/36] meson: Introduce meson_user_arch source set for arch-specific user-mode, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 18/36] target/mips: Introduce tcg-internal.h for TCG specific declarations, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 19/36] target/mips: Add simple user-mode mips_cpu_do_interrupt(), Philippe Mathieu-Daudé, 2021/05/02
- [PULL 20/36] target/mips: Add simple user-mode mips_cpu_tlb_fill(), Philippe Mathieu-Daudé, 2021/05/02
- [PULL 21/36] target/mips: Move cpu_signal_handler definition around, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 22/36] target/mips: Move sysemu specific files under sysemu/ subfolder, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 23/36] target/mips: Move physical addressing code to sysemu/physaddr.c, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 24/36] target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 26/36] target/mips: Restrict mmu_init() to TCG, Philippe Mathieu-Daudé, 2021/05/02