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[PULL 02/36] target/mips: Fix CACHEE opcode (CACHE using EVA addressing)
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 02/36] target/mips: Fix CACHEE opcode (CACHE using EVA addressing) |
Date: |
Sun, 2 May 2021 18:15:04 +0200 |
The CACHEE opcode "requires CP0 privilege".
The pseudocode checks in the ISA manual is:
if is_eva and not C0.Config5.EVA:
raise exception('RI')
if not IsCoprocessor0Enabled():
raise coprocessor_exception(0)
Add the missing checks.
Inspired-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210420175426.1875746-1-f4bug@amsat.org>
---
target/mips/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 71fa5ec1973..5dad75cdf37 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -20957,6 +20957,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
gen_ld(ctx, OPC_LHUE, rt, rs, s);
break;
case NM_CACHEE:
+ check_eva(ctx);
+ check_cp0_enabled(ctx);
check_nms_dl_il_sl_tl_l2c(ctx);
gen_cache_operation(ctx, rt, rs, s);
break;
@@ -24530,11 +24532,11 @@ static void decode_opc_special3(CPUMIPSState *env,
DisasContext *ctx)
gen_st_cond(ctx, rt, rs, imm, MO_TESL, true);
return;
case OPC_CACHEE:
+ check_eva(ctx);
check_cp0_enabled(ctx);
if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
gen_cache_operation(ctx, rt, rs, imm);
}
- /* Treat as NOP. */
return;
case OPC_PREFE:
check_cp0_enabled(ctx);
--
2.26.3
- [PULL 00/36] MIPS patches for 2021-05-02, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 01/36] hw/isa/piix4: Use qdev_get_gpio_in_named() to get ISA IRQ, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 02/36] target/mips: Fix CACHEE opcode (CACHE using EVA addressing),
Philippe Mathieu-Daudé <=
- [PULL 03/36] target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 04/36] target/mips: Remove spurious LOG_UNIMP of MTHC0 opcode, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 05/36] target/mips: Migrate missing CPU fields, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 06/36] target/mips: Make check_cp0_enabled() return a boolean, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 07/36] target/mips: Simplify meson TCG rules, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 08/36] target/mips: Move IEEE rounding mode array to new source file, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 09/36] target/mips: Move msa_reset() to new source file, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 10/36] target/mips: Make CPU/FPU regnames[] arrays global, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 11/36] target/mips: Optimize CPU/FPU regnames[] arrays, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 12/36] target/mips: Restrict mips_cpu_dump_state() to cpu.c, Philippe Mathieu-Daudé, 2021/05/02