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Re: [PATCH v2 3/5] target/arm: Handle trapping to EL2 of AArch32 VMRS in
Re: [PATCH v2 3/5] target/arm: Handle trapping to EL2 of AArch32 VMRS instructions
Mon, 2 Dec 2019 07:35:25 -0800
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On 12/1/19 12:20 PM, Marc Zyngier wrote:
> HCR_EL2.TID3 requires that AArch32 reads of MVFR are trapped to
> EL2, and HCR_EL2.TID0 does the same for reads of FPSID.
> In order to handle this, introduce a new TCG helper function that
> checks for these control bits before executing the VMRC instruction.
> Tested with a hacked-up version of KVM/arm64 that sets the control
> bits for 32bit guests.
> Reviewed-by: Edgar E. Iglesias <address@hidden>
> Signed-off-by: Marc Zyngier <address@hidden>
> target/arm/helper-a64.h | 2 ++
> target/arm/translate-vfp.inc.c | 18 +++++++++++++++---
> target/arm/vfp_helper.c | 29 +++++++++++++++++++++++++++++
> 3 files changed, 46 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson <address@hidden>
Annoying that there's a bug in the manual -- FPSID is listed as group 0 in
plenty of places, except in the pseudo-code for Accessing the FPSID which uses
[PATCH v2 2/5] target/arm: Honor HCR_EL2.TID1 trapping requirements, Marc Zyngier, 2019/12/01
[PATCH v2 4/5] target/arm: Handle AArch32 CP15 trapping via HSTR_EL2, Marc Zyngier, 2019/12/01