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[PATCH v2 0/5] target/arm: More EL2 trapping fixes

From: Marc Zyngier
Subject: [PATCH v2 0/5] target/arm: More EL2 trapping fixes
Date: Sun, 1 Dec 2019 12:20:13 +0000

Hi all,

This series is a follow-up on [1], which tried to address the
remaining missing HCR_EL2.TIDx traps. I've hopefully now adressed the
comments that Peter and Edgar raised.

I've also tried to tackle missing traps generated by HSTR_EL2, which
got completely ignored so far. Note that this results in the use of a
new TB bit, which I understand is a rare resource. I'd welcome
comments on how to handle it differently if at all possible.

Finally, and as a bonus non-feature, I've added support for the
missing Jazelle registers, giving me the opportunity to allow trapping
of JIDR to EL2 using HCR_EL2.TID0. Yay, Christmas! ;-)

I'm now going back to kernel stuff. I swear!

[1] https://patchew.org/QEMU/address@hidden/

Marc Zyngier (5):
  target/arm: Honor HCR_EL2.TID2 trapping requirements
  target/arm: Honor HCR_EL2.TID1 trapping requirements
  target/arm: Handle trapping to EL2 of AArch32 VMRS instructions
  target/arm: Handle AArch32 CP15 trapping via HSTR_EL2
  target/arm: Add support for missing Jazelle system registers

 target/arm/cpu.h               |   2 +
 target/arm/helper-a64.h        |   2 +
 target/arm/helper.c            | 100 ++++++++++++++++++++++++++++++---
 target/arm/op_helper.c         |  21 +++++++
 target/arm/translate-vfp.inc.c |  18 +++++-
 target/arm/translate.c         |   3 +-
 target/arm/translate.h         |   2 +
 target/arm/vfp_helper.c        |  29 ++++++++++
 8 files changed, 165 insertions(+), 12 deletions(-)


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