Re: [Qemu-devel] RFC: Why does target/m68k RTE insn. use gen_exception

[Lucien Anti-Spam]

   >On Monday, July 1, 2019, 06:10:55 PM GMT+9, Peter Maydell <address@hidden> 
wrote: > > On Sat, 29 Jun 2019 at 17:37, Lucien Murray-Pitts> > 
<address@hidden> wrote:
> > However for the m68k the do_transaction_failed function pointer field
> > has not been implemented.>Er, I implemented that in commit 
> > e1aaf3a88e95ab007. Are
>you working with an out-of-date version of QEMU ?

Sorry not pulled in a long time, you are right that is there now - I dont 
generally check the development list outside of replies, and was focused on the 
stepping issue - I will be more careful of that in future.  Thanks for the 
heads up.
Further to my initial problem I noticed that TRAP #0 also jumps to the handlers 
+1 instruction.  Same behavior can also be seen with ARM "SWI #0".    (PC shows 
0x0C vs the expected 0x08)
Putting a "BRA $" / "B $" so that it loops on the first address of the handler 
results in the step stopping, of course, at the expected "first instruction" of 
the vector handler.
So it would seem this maybe a wider problem than just the m68K.Since I dont 
really understand the TCG complete execution method, and how it fits in with 
the GNU RSP "s" step command I am going to take some time to work this out.
I appreciate any hints people can provide, but I dont mind plugging away - I am 
learning and surprising myself how much there is to this.
Cheers,Luc