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Re: [Qemu-devel] RFC: Why does target/m68k RTE insn. use gen_exception


From: Peter Maydell
Subject: Re: [Qemu-devel] RFC: Why does target/m68k RTE insn. use gen_exception
Date: Thu, 11 Jul 2019 10:00:19 +0100

On Wed, 10 Jul 2019 at 19:15, Alex Bennée <address@hidden> wrote:
> Lucien Murray-Pitts <address@hidden> writes:
> > I am very new to TCG, so it does seem there is a lot of code in the
> > translator_loop that appears to be interacting with the CPU model/state.
> > Should I be worried about this, or is this a safe function to call outside
> > of the translator core proper?
>
> I would recommend against it - the time to do stuff like this would be
> during translation phase where you can save the data. Don't re-invoke the
> translator while trying to process an exception.
>
> Is the instruction format that irregular that you can't do a simple
> disassembly in a helper?

For anything moderately complicated, the use of the tcg_set_insn_param()
and restore_state_to_opc() that RTH recommends is definitely the
way to go. That way you can just save the right information when
you translate the code and don't have two separate bits of decoding
logic that need to agree.

For a more complicated example than the s390 one, you can look
at target/arm, which uses this to generate the 'syndrome' register
value which can include things like "which register was this faulting
load trying to load to".

thanks
-- PMM



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