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[Qemu-devel] [PULL 04/28] target-arm: Don't try to set ESR IL bit in arm
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 04/28] target-arm: Don't try to set ESR IL bit in arm_cpu_do_interrupt_aarch64() |
Date: |
Mon, 6 Jun 2016 15:47:21 +0100 |
Remove some incorrect code from arm_cpu_do_interrupt_aarch64()
which attempts to set the IL bit in the syndrome register based
on the value of env->thumb. This is wrong in several ways:
* IL doesn't indicate Thumb-vs-ARM, it indicates instruction
length (which may be 16 or 32 for Thumb and is always 32 for ARM)
* not every syndrome format uses IL like this -- for some IL is
always set, and for some it is always clear
* the code is changing esr_el[new_el] even for interrupt entry,
which is not supposed to modify ESR_ELx at all
Delete the code, and instead rely on the syndrome value in
env->exception.syndrome having already been set up with the
correct value of IL.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
---
target-arm/helper.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 9a6ff2e..86a094d 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -6365,9 +6365,6 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
env->elr_el[new_el] = env->pc;
} else {
env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env);
- if (!env->thumb) {
- env->cp15.esr_el[new_el] |= 1 << 25;
- }
env->elr_el[new_el] = env->regs[15];
aarch64_sync_32_to_64(env);
--
1.9.1
- [Qemu-devel] [PULL 07/28] hw/arm/virt: Add PMU node for virt machine, (continued)
- [Qemu-devel] [PULL 07/28] hw/arm/virt: Add PMU node for virt machine, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 01/28] target-arm: Add the HSTR_EL2 register, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 02/28] target-arm: A64: Create Instruction Syndromes for Data Aborts, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 08/28] hw/arm/virt-acpi-build: Add PMU IRQ number in ACPI table, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 12/28] xlnx-zynqmp: Add a secure prop to en/disable ARM Security Extensions, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 05/28] hw/arm/virt: fix limit of 64-bit ACPI/ECAM PCI MMIO range, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 03/28] target-arm: Set IL bit in syndromes for insn abort, watchpoint, swstep, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 13/28] xlnx-zynqmp: Make the RPU subsystem optional, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 14/28] xlnx-zynqmp: Delay realization of GIC until post CPU realization, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 20/28] hw/ptimer: Introduce ptimer_get_limit, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 04/28] target-arm: Don't try to set ESR IL bit in arm_cpu_do_interrupt_aarch64(),
Peter Maydell <=
- [Qemu-devel] [PULL 23/28] hw/char: QOM'ify digic-uart model, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 28/28] zynqmp: Add the ZCU102 board, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 27/28] target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translation, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 21/28] hw/char: QOM'ify pl011 model, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 22/28] hw/char: QOM'ify cadence_uart model, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 25/28] hw/char: QOM'ify xilinx_uartlite model, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 10/28] i2c: add aspeed i2c controller, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 18/28] hw/ptimer: Update .delta on period/freq change, Peter Maydell, 2016/06/06