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[Qemu-devel] [PULL 13/28] xlnx-zynqmp: Make the RPU subsystem optional
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 13/28] xlnx-zynqmp: Make the RPU subsystem optional |
Date: |
Mon, 6 Jun 2016 15:47:30 +0100 |
From: "Edgar E. Iglesias" <address@hidden>
The way we currently model the RPU subsystem is of quite
limited use. In addition to that, it causes problems for
KVM and for GDB debugging.
Make the RPU optional by adding a has_rpu property and
default to having it disabled.
This changes the default setup from having the RPU to not
longer having it.
Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/xlnx-zynqmp.c | 62 +++++++++++++++++++++++++++-----------------
include/hw/arm/xlnx-zynqmp.h | 2 ++
2 files changed, 40 insertions(+), 24 deletions(-)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 965a250..3a8af6a 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -83,6 +83,41 @@ static inline int arm_gic_ppi_index(int cpu_nr, int
ppi_index)
return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
}
+static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu,
+ Error **errp)
+{
+ Error *err = NULL;
+ int i;
+
+ for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
+ char *name;
+
+ object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
+ "cortex-r5-" TYPE_ARM_CPU);
+ object_property_add_child(OBJECT(s), "rpu-cpu[*]",
+ OBJECT(&s->rpu_cpu[i]), &error_abort);
+
+ name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
+ if (strcmp(name, boot_cpu)) {
+ /* Secondary CPUs start in PSCI powered-down state */
+ object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
+ "start-powered-off", &error_abort);
+ } else {
+ s->boot_cpu_ptr = &s->rpu_cpu[i];
+ }
+ g_free(name);
+
+ object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
+ &error_abort);
+ object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
+ &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ }
+}
+
static void xlnx_zynqmp_init(Object *obj)
{
XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
@@ -95,13 +130,6 @@ static void xlnx_zynqmp_init(Object *obj)
&error_abort);
}
- for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
- object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
- "cortex-r5-" TYPE_ARM_CPU);
- object_property_add_child(obj, "rpu-cpu[*]", OBJECT(&s->rpu_cpu[i]),
- &error_abort);
- }
-
object_property_add_link(obj, "ddr-ram", TYPE_MEMORY_REGION,
(Object **)&s->ddr_ram,
qdev_prop_allow_set_link_before_realize,
@@ -260,23 +288,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error
**errp)
qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
}
- for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
- char *name;
-
- name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
- if (strcmp(name, boot_cpu)) {
- /* Secondary CPUs start in PSCI powered-down state */
- object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
- "start-powered-off", &error_abort);
- } else {
- s->boot_cpu_ptr = &s->rpu_cpu[i];
- }
- g_free(name);
-
- object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
- &error_abort);
- object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
- &err);
+ if (s->has_rpu) {
+ xlnx_zynqmp_create_rpu(s, boot_cpu, &err);
if (err) {
error_propagate(errp, err);
return;
@@ -373,6 +386,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error
**errp)
static Property xlnx_zynqmp_props[] = {
DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
+ DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
DEFINE_PROP_END_OF_LIST()
};
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 38d4c8c..68f6eb0 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -87,6 +87,8 @@ typedef struct XlnxZynqMPState {
/* Has the ARM Security extensions? */
bool secure;
+ /* Has the RPU subsystem? */
+ bool has_rpu;
} XlnxZynqMPState;
#define XLNX_ZYNQMP_H
--
1.9.1
- [Qemu-devel] [PULL 09/28] hw/intc/gic: RAZ/WI non-sec access to sec interrupts, (continued)
- [Qemu-devel] [PULL 09/28] hw/intc/gic: RAZ/WI non-sec access to sec interrupts, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 26/28] char: get rid of qemu_char_get_next_serial, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 24/28] hw/char: QOM'ify stm32f2xx_usart model, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 07/28] hw/arm/virt: Add PMU node for virt machine, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 01/28] target-arm: Add the HSTR_EL2 register, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 02/28] target-arm: A64: Create Instruction Syndromes for Data Aborts, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 08/28] hw/arm/virt-acpi-build: Add PMU IRQ number in ACPI table, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 12/28] xlnx-zynqmp: Add a secure prop to en/disable ARM Security Extensions, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 05/28] hw/arm/virt: fix limit of 64-bit ACPI/ECAM PCI MMIO range, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 03/28] target-arm: Set IL bit in syndromes for insn abort, watchpoint, swstep, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 13/28] xlnx-zynqmp: Make the RPU subsystem optional,
Peter Maydell <=
- [Qemu-devel] [PULL 14/28] xlnx-zynqmp: Delay realization of GIC until post CPU realization, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 20/28] hw/ptimer: Introduce ptimer_get_limit, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 04/28] target-arm: Don't try to set ESR IL bit in arm_cpu_do_interrupt_aarch64(), Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 23/28] hw/char: QOM'ify digic-uart model, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 28/28] zynqmp: Add the ZCU102 board, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 27/28] target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translation, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 21/28] hw/char: QOM'ify pl011 model, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 22/28] hw/char: QOM'ify cadence_uart model, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 25/28] hw/char: QOM'ify xilinx_uartlite model, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 10/28] i2c: add aspeed i2c controller, Peter Maydell, 2016/06/06