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[Qemu-devel] [PULL 12/28] xlnx-zynqmp: Add a secure prop to en/disable A
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 12/28] xlnx-zynqmp: Add a secure prop to en/disable ARM Security Extensions |
Date: |
Mon, 6 Jun 2016 15:47:29 +0100 |
From: "Edgar E. Iglesias" <address@hidden>
Add a secure prop to en/disable ARM Security Extensions.
This is particularly useful for KVM runs.
Default to disabled to match the behavior of KVM.
This changes the default setup from having the ARM Security
Extensions to not longer having them.
Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/xlnx-zynqmp.c | 3 +++
include/hw/arm/xlnx-zynqmp.h | 3 +++
2 files changed, 6 insertions(+)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 4d504da..965a250 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -238,6 +238,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error
**errp)
}
g_free(name);
+ object_property_set_bool(OBJECT(&s->apu_cpu[i]),
+ s->secure, "has_el3", NULL);
object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
"reset-cbar", &error_abort);
object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
@@ -370,6 +372,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error
**errp)
static Property xlnx_zynqmp_props[] = {
DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
+ DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
DEFINE_PROP_END_OF_LIST()
};
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 2332596..38d4c8c 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -84,6 +84,9 @@ typedef struct XlnxZynqMPState {
char *boot_cpu;
ARMCPU *boot_cpu_ptr;
+
+ /* Has the ARM Security extensions? */
+ bool secure;
} XlnxZynqMPState;
#define XLNX_ZYNQMP_H
--
1.9.1
- [Qemu-devel] [PULL 19/28] hw/ptimer: Support "on the fly" timer mode switch, (continued)
- [Qemu-devel] [PULL 19/28] hw/ptimer: Support "on the fly" timer mode switch, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 11/28] hw/arm/virt: Reject gic-version=host for non-KVM, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 06/28] target-arm: kvm64: set guest PMUv3 feature bit if supported, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 09/28] hw/intc/gic: RAZ/WI non-sec access to sec interrupts, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 26/28] char: get rid of qemu_char_get_next_serial, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 24/28] hw/char: QOM'ify stm32f2xx_usart model, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 07/28] hw/arm/virt: Add PMU node for virt machine, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 01/28] target-arm: Add the HSTR_EL2 register, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 02/28] target-arm: A64: Create Instruction Syndromes for Data Aborts, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 08/28] hw/arm/virt-acpi-build: Add PMU IRQ number in ACPI table, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 12/28] xlnx-zynqmp: Add a secure prop to en/disable ARM Security Extensions,
Peter Maydell <=
- [Qemu-devel] [PULL 05/28] hw/arm/virt: fix limit of 64-bit ACPI/ECAM PCI MMIO range, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 03/28] target-arm: Set IL bit in syndromes for insn abort, watchpoint, swstep, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 13/28] xlnx-zynqmp: Make the RPU subsystem optional, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 14/28] xlnx-zynqmp: Delay realization of GIC until post CPU realization, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 20/28] hw/ptimer: Introduce ptimer_get_limit, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 04/28] target-arm: Don't try to set ESR IL bit in arm_cpu_do_interrupt_aarch64(), Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 23/28] hw/char: QOM'ify digic-uart model, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 28/28] zynqmp: Add the ZCU102 board, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 27/28] target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translation, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 21/28] hw/char: QOM'ify pl011 model, Peter Maydell, 2016/06/06