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[Qemu-devel] [PULL 20/28] hw/ptimer: Introduce ptimer_get_limit
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 20/28] hw/ptimer: Introduce ptimer_get_limit |
Date: |
Mon, 6 Jun 2016 15:47:37 +0100 |
From: Dmitry Osipenko <address@hidden>
Currently ptimer users are used to store copy of the limit value, because
ptimer doesn't provide facility to retrieve the limit. Let's provide it.
Signed-off-by: Dmitry Osipenko <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/core/ptimer.c | 5 +++++
include/hw/ptimer.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c
index d0b2f38..05b0c27 100644
--- a/hw/core/ptimer.c
+++ b/hw/core/ptimer.c
@@ -225,6 +225,11 @@ void ptimer_set_limit(ptimer_state *s, uint64_t limit, int
reload)
}
}
+uint64_t ptimer_get_limit(ptimer_state *s)
+{
+ return s->limit;
+}
+
const VMStateDescription vmstate_ptimer = {
.name = "ptimer",
.version_id = 1,
diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h
index 8ebacbb..e397db5 100644
--- a/include/hw/ptimer.h
+++ b/include/hw/ptimer.h
@@ -19,6 +19,7 @@ typedef void (*ptimer_cb)(void *opaque);
ptimer_state *ptimer_init(QEMUBH *bh);
void ptimer_set_period(ptimer_state *s, int64_t period);
void ptimer_set_freq(ptimer_state *s, uint32_t freq);
+uint64_t ptimer_get_limit(ptimer_state *s);
void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
uint64_t ptimer_get_count(ptimer_state *s);
void ptimer_set_count(ptimer_state *s, uint64_t count);
--
1.9.1
- [Qemu-devel] [PULL 24/28] hw/char: QOM'ify stm32f2xx_usart model, (continued)
- [Qemu-devel] [PULL 24/28] hw/char: QOM'ify stm32f2xx_usart model, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 07/28] hw/arm/virt: Add PMU node for virt machine, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 01/28] target-arm: Add the HSTR_EL2 register, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 02/28] target-arm: A64: Create Instruction Syndromes for Data Aborts, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 08/28] hw/arm/virt-acpi-build: Add PMU IRQ number in ACPI table, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 12/28] xlnx-zynqmp: Add a secure prop to en/disable ARM Security Extensions, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 05/28] hw/arm/virt: fix limit of 64-bit ACPI/ECAM PCI MMIO range, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 03/28] target-arm: Set IL bit in syndromes for insn abort, watchpoint, swstep, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 13/28] xlnx-zynqmp: Make the RPU subsystem optional, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 14/28] xlnx-zynqmp: Delay realization of GIC until post CPU realization, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 20/28] hw/ptimer: Introduce ptimer_get_limit,
Peter Maydell <=
- [Qemu-devel] [PULL 04/28] target-arm: Don't try to set ESR IL bit in arm_cpu_do_interrupt_aarch64(), Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 23/28] hw/char: QOM'ify digic-uart model, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 28/28] zynqmp: Add the ZCU102 board, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 27/28] target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translation, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 21/28] hw/char: QOM'ify pl011 model, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 22/28] hw/char: QOM'ify cadence_uart model, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 25/28] hw/char: QOM'ify xilinx_uartlite model, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 10/28] i2c: add aspeed i2c controller, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 18/28] hw/ptimer: Update .delta on period/freq change, Peter Maydell, 2016/06/06