[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 22/28] hw/char: QOM'ify cadence_uart model
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 22/28] hw/char: QOM'ify cadence_uart model |
Date: |
Mon, 6 Jun 2016 15:47:39 +0100 |
From: xiaoqiang zhao <address@hidden>
* drop qemu_char_get_next_serial and use chardev prop
* create cadence_uart_create wrapper function to create
cadence_uart_device
* change affected board code to use the new way
Signed-off-by: xiaoqiang zhao <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/xilinx_zynq.c | 5 +++--
hw/arm/xlnx-zynqmp.c | 1 +
hw/char/cadence_uart.c | 13 +++++++------
include/hw/char/cadence_uart.h | 17 +++++++++++++++++
4 files changed, 28 insertions(+), 8 deletions(-)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 98b17c9..aefebcf 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -32,6 +32,7 @@
#include "hw/ssi/ssi.h"
#include "qemu/error-report.h"
#include "hw/sd/sd.h"
+#include "hw/char/cadence_uart.h"
#define NUM_SPI_FLASHES 4
#define NUM_QSPI_FLASHES 2
@@ -235,8 +236,8 @@ static void zynq_init(MachineState *machine)
sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]);
sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]);
- sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]);
- sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]);
+ cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hds[0]);
+ cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hds[1]);
sysbus_create_varargs("cadence_ttc", 0xF8001000,
pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 9a1bc94..308d677 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -331,6 +331,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error
**errp)
}
for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
+ qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]);
object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
if (err) {
error_propagate(errp, err);
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index 442dac5..c856fc3 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -468,9 +468,6 @@ static void cadence_uart_realize(DeviceState *dev, Error
**errp)
s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
fifo_trigger_update, s);
- /* FIXME use a qdev chardev prop instead of qemu_char_get_next_serial() */
- s->chr = qemu_char_get_next_serial();
-
if (s->chr) {
qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive,
uart_event, s);
@@ -517,6 +514,11 @@ static const VMStateDescription vmstate_cadence_uart = {
}
};
+static Property cadence_uart_properties[] = {
+ DEFINE_PROP_CHR("chardev", CadenceUARTState, chr),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void cadence_uart_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -524,9 +526,8 @@ static void cadence_uart_class_init(ObjectClass *klass,
void *data)
dc->realize = cadence_uart_realize;
dc->vmsd = &vmstate_cadence_uart;
dc->reset = cadence_uart_reset;
- /* Reason: realize() method uses qemu_char_get_next_serial() */
- dc->cannot_instantiate_with_device_add_yet = true;
-}
+ dc->props = cadence_uart_properties;
+ }
static const TypeInfo cadence_uart_info = {
.name = TYPE_CADENCE_UART,
diff --git a/include/hw/char/cadence_uart.h b/include/hw/char/cadence_uart.h
index 6310f52..a12773c 100644
--- a/include/hw/char/cadence_uart.h
+++ b/include/hw/char/cadence_uart.h
@@ -49,5 +49,22 @@ typedef struct {
QEMUTimer *fifo_trigger_handle;
} CadenceUARTState;
+static inline DeviceState *cadence_uart_create(hwaddr addr,
+ qemu_irq irq,
+ CharDriverState *chr)
+{
+ DeviceState *dev;
+ SysBusDevice *s;
+
+ dev = qdev_create(NULL, TYPE_CADENCE_UART);
+ s = SYS_BUS_DEVICE(dev);
+ qdev_prop_set_chr(dev, "chardev", chr);
+ qdev_init_nofail(dev);
+ sysbus_mmio_map(s, 0, addr);
+ sysbus_connect_irq(s, 0, irq);
+
+ return dev;
+}
+
#define CADENCE_UART_H
#endif
--
1.9.1
- [Qemu-devel] [PULL 05/28] hw/arm/virt: fix limit of 64-bit ACPI/ECAM PCI MMIO range, (continued)
- [Qemu-devel] [PULL 05/28] hw/arm/virt: fix limit of 64-bit ACPI/ECAM PCI MMIO range, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 03/28] target-arm: Set IL bit in syndromes for insn abort, watchpoint, swstep, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 13/28] xlnx-zynqmp: Make the RPU subsystem optional, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 14/28] xlnx-zynqmp: Delay realization of GIC until post CPU realization, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 20/28] hw/ptimer: Introduce ptimer_get_limit, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 04/28] target-arm: Don't try to set ESR IL bit in arm_cpu_do_interrupt_aarch64(), Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 23/28] hw/char: QOM'ify digic-uart model, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 28/28] zynqmp: Add the ZCU102 board, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 27/28] target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translation, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 21/28] hw/char: QOM'ify pl011 model, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 22/28] hw/char: QOM'ify cadence_uart model,
Peter Maydell <=
- [Qemu-devel] [PULL 25/28] hw/char: QOM'ify xilinx_uartlite model, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 10/28] i2c: add aspeed i2c controller, Peter Maydell, 2016/06/06
- [Qemu-devel] [PULL 18/28] hw/ptimer: Update .delta on period/freq change, Peter Maydell, 2016/06/06