Re: [Simulavr-devel] repositories

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On Wed Aug 26 12:36 , Thomas Klepp  sent:

>
>> What are the other important differences between the CVS and git versions?
>
>What more? There is the verilog extension, but you'll not get it, if you 
>havn't verilog installed and enabled. That's a extension like the python 
>module, it dosn't modify the core code. I have rewritten timer code, 
>that's a big block. Now all available devices have full timer support. 
>In the moment I write tests for timers and maybe there are some things, 
>which have to make better or (hopefully not) bugs.
>
>Then, there is a feature to write VCD-traces while simulation is 
>running. I use that for example for timertests. Look at 
>regress/timertest. This runs a simple AVR test program in simulavr and 
>writes out a vcd file. This will be analysed in a python unittest. If 
>you go to regress/timertest and run "make check", you can see that in 
>action. If you have installed gtkwave, then you could view the traced 
>data, for example, see, when a interrupt is started an how long it runs, 
>how the timer counter changes, look at the ports, how they are changed 
>by ocr output generators from timer and so one. This is now also multi 
>core ready. (but simulavr supports current only one core, for that it's 
>necessary to use the python module)

Wow.
That is a lot.
'Twould be nice to hear from the maintainers.
There is a lot of synchronization to do.

--
Michael Hennebry
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"War is only a hobby."
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