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Re: [Qemu-ppc] [RFC PATCH 00/17] target/ppc: Implement POWER9 pseries tc
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [RFC PATCH 00/17] target/ppc: Implement POWER9 pseries tcg legacy kernel support |
Date: |
Wed, 1 Feb 2017 13:22:59 +1100 |
User-agent: |
Mutt/1.7.1 (2016-10-04) |
On Wed, Feb 01, 2017 at 01:16:00PM +1100, David Gibson wrote:
> On Fri, Jan 13, 2017 at 05:28:06PM +1100, Suraj Jitindar Singh wrote:
> > This patch set provides the initial implementation of support for the
> > POWER9 processor running in tcg mode under the pseries machine type.
> >
> > To use a POWER9 cpu provide the command line option "-cpu POWER9".
> >
> > This is the initial work to make the mmu emulation model look like a POWER9
> >
> > Currently only legacy kernels are supported (hash without segment tables).
> >
> > This patch set will be followed by two more in the near future to support
> > the new process table capabilities added in ISAv3.00; hash via segment
> > tables and radix. Kernels with support for this will currently fail when
> > they try to register a process table as this isn't yet implemented.
> >
> > The assumption is that we're running a legacy kernel, in the event the
> > guest registers a process table (when support exists) we will handle it
> > accordingly.
> >
> > The main changes are:
> > - Define a new mmu model and fault handler
> > - Add new LPCR fields and check them accordingly
> > - Add a partition table entry to the machine state
> > - Point to the partition table entry in the cpu state
> > - Remove SDR1
> > - Adapt to new pte format
> > - NOOP the cp_abort instruction
> > - Small bug fixes
> >
> > This was intially one huge patch so I've tried to break it up into what I
> > think are logical chunks, how exactly this should be split up is up for
> > debate.
> >
> > A current upstream kernel with POWER9 support added to the architecture
> > vector should correctly report a POWER9 cpu under /proc/cpuinfo.
>
> I've merged 14-16/17 since they seem to stand on their own as fixes.
And 17/17 as well.
>
> >
> > Suraj Jitindar Singh (17):
> > powerpc/cpu-models: rename ISAv3.00 logical PVR definition
> > hw/ppc/spapr: Add POWER9 to pseries cpu models
> > target/ppc: Add pcr_supported to POWER9 cpu class definition
> > target/ppc/POWER9: Add ISAv3.00 MMU definition
> > target/ppc/POWER9: Adapt LPCR handling for POWER9
> > target/ppc/POWER9: Direct all instr and data storage interrupts to the
> > hypv
> > target/ppc/POWER9: Add partition table pointer to sPAPRMachineState
> > target/ppc/POWER9: Add external partition table pointer to cpu state
> > target/ppc/POWER9: Remove SDR1 register
> > target/ppc/POWER9: Add POWER9 mmu fault handler
> > target/ppc/POWER9: Update to new pte format for POWER9 accesses
> > target/ppc/POWER9: Add POWER9 pa-features definition
> > target/ppc/POWER9: Add cpu_has_work function for POWER9
> > target/ppc/debug: Print LPCR register value if register exists
> > tcg/POWER9: NOOP the cp_abort instruction
> > target/ppc/mmu_hash64: Fix printing unsigned as signed int
> > target/ppc/mmu_hash64: Fix incorrect shift value in amr calculation
> >
> > hw/ppc/spapr.c | 56 ++++++++++++++++++++++++---
> > hw/ppc/spapr_cpu_core.c | 15 +++++++-
> > hw/ppc/spapr_hcall.c | 51 +++++++++++++------------
> > include/hw/ppc/spapr.h | 1 +
> > target/ppc/cpu-models.h | 2 +-
> > target/ppc/cpu-qom.h | 5 ++-
> > target/ppc/cpu.h | 24 +++++++++++-
> > target/ppc/kvm.c | 10 ++++-
> > target/ppc/mmu-hash64.c | 68 +++++++++++++++++++++++++++------
> > target/ppc/mmu-hash64.h | 73 +++++++++++++++++++++++++----------
> > target/ppc/mmu.h | 27 +++++++++++++
> > target/ppc/mmu_helper.c | 61 ++++++++++++++++++++++++++++++
> > target/ppc/translate.c | 14 ++++++-
> > target/ppc/translate_init.c | 92
> > +++++++++++++++++++++++++++++++++++++++------
> > 14 files changed, 418 insertions(+), 81 deletions(-)
> > create mode 100644 target/ppc/mmu.h
> >
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-ppc] [RFC PATCH 12/17] target/ppc/POWER9: Add POWER9 pa-features definition, (continued)
- [Qemu-ppc] [RFC PATCH 12/17] target/ppc/POWER9: Add POWER9 pa-features definition, Suraj Jitindar Singh, 2017/01/13
- [Qemu-ppc] [RFC PATCH 11/17] target/ppc/POWER9: Update to new pte format for POWER9 accesses, Suraj Jitindar Singh, 2017/01/13
- [Qemu-ppc] [RFC PATCH 13/17] target/ppc/POWER9: Add cpu_has_work function for POWER9, Suraj Jitindar Singh, 2017/01/13
- [Qemu-ppc] [RFC PATCH 14/17] target/ppc/debug: Print LPCR register value if register exists, Suraj Jitindar Singh, 2017/01/13
- [Qemu-ppc] [RFC PATCH 15/17] tcg/POWER9: NOOP the cp_abort instruction, Suraj Jitindar Singh, 2017/01/13
- [Qemu-ppc] [RFC PATCH 16/17] target/ppc/mmu_hash64: Fix printing unsigned as signed int, Suraj Jitindar Singh, 2017/01/13
- [Qemu-ppc] [RFC PATCH 17/17] target/ppc/mmu_hash64: Fix incorrect shift value in amr calculation, Suraj Jitindar Singh, 2017/01/13
- Re: [Qemu-ppc] [Qemu-devel] [RFC PATCH 00/17] target/ppc: Implement POWER9 pseries tcg legacy kernel support, no-reply, 2017/01/13
- Re: [Qemu-ppc] [RFC PATCH 00/17] target/ppc: Implement POWER9 pseries tcg legacy kernel support, David Gibson, 2017/01/31
- Re: [Qemu-ppc] [RFC PATCH 00/17] target/ppc: Implement POWER9 pseries tcg legacy kernel support,
David Gibson <=