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[Qemu-ppc] [RFC PATCH 15/17] tcg/POWER9: NOOP the cp_abort instruction
From: |
Suraj Jitindar Singh |
Subject: |
[Qemu-ppc] [RFC PATCH 15/17] tcg/POWER9: NOOP the cp_abort instruction |
Date: |
Fri, 13 Jan 2017 17:28:21 +1100 |
The cp_abort instruction is used to remove the state of an in progress
copy paste sequence. POWER9 compilers add this in various places, such
as context switches which causes illegal instruction signals since we
don't yet implement this instruction.
Given there is no implementation of the copy paste facility and that we
don't claim to support it, we can just noop this instruction.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
---
target/ppc/translate.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 5d63254..7527bd2 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6166,6 +6166,10 @@ GEN_TM_NOOP(tabortwci);
GEN_TM_NOOP(tabortdc);
GEN_TM_NOOP(tabortdci);
GEN_TM_NOOP(tsr);
+static inline void gen_cp_abort(DisasContext *ctx)
+{
+ // Do Nothing
+}
static void gen_tcheck(DisasContext *ctx)
{
@@ -6255,6 +6259,7 @@ GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF,
0x00000000, PPC_INTEGER),
GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
--
2.5.5
- [Qemu-ppc] [RFC PATCH 06/17] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv, (continued)
- [Qemu-ppc] [RFC PATCH 06/17] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv, Suraj Jitindar Singh, 2017/01/13
- [Qemu-ppc] [RFC PATCH 08/17] target/ppc/POWER9: Add external partition table pointer to cpu state, Suraj Jitindar Singh, 2017/01/13
- [Qemu-ppc] [RFC PATCH 07/17] target/ppc/POWER9: Add partition table pointer to sPAPRMachineState, Suraj Jitindar Singh, 2017/01/13
- [Qemu-ppc] [RFC PATCH 09/17] target/ppc/POWER9: Remove SDR1 register, Suraj Jitindar Singh, 2017/01/13
- [Qemu-ppc] [RFC PATCH 10/17] target/ppc/POWER9: Add POWER9 mmu fault handler, Suraj Jitindar Singh, 2017/01/13
- [Qemu-ppc] [RFC PATCH 12/17] target/ppc/POWER9: Add POWER9 pa-features definition, Suraj Jitindar Singh, 2017/01/13
- [Qemu-ppc] [RFC PATCH 11/17] target/ppc/POWER9: Update to new pte format for POWER9 accesses, Suraj Jitindar Singh, 2017/01/13
- [Qemu-ppc] [RFC PATCH 13/17] target/ppc/POWER9: Add cpu_has_work function for POWER9, Suraj Jitindar Singh, 2017/01/13
- [Qemu-ppc] [RFC PATCH 14/17] target/ppc/debug: Print LPCR register value if register exists, Suraj Jitindar Singh, 2017/01/13
- [Qemu-ppc] [RFC PATCH 15/17] tcg/POWER9: NOOP the cp_abort instruction,
Suraj Jitindar Singh <=
- [Qemu-ppc] [RFC PATCH 16/17] target/ppc/mmu_hash64: Fix printing unsigned as signed int, Suraj Jitindar Singh, 2017/01/13
- [Qemu-ppc] [RFC PATCH 17/17] target/ppc/mmu_hash64: Fix incorrect shift value in amr calculation, Suraj Jitindar Singh, 2017/01/13
- Re: [Qemu-ppc] [Qemu-devel] [RFC PATCH 00/17] target/ppc: Implement POWER9 pseries tcg legacy kernel support, no-reply, 2017/01/13
- Re: [Qemu-ppc] [RFC PATCH 00/17] target/ppc: Implement POWER9 pseries tcg legacy kernel support, David Gibson, 2017/01/31