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[Qemu-ppc] [PATCH 05/11] target-ppc: Add xviexpsp instruction
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [PATCH 05/11] target-ppc: Add xviexpsp instruction |
Date: |
Tue, 10 Jan 2017 14:20:37 +0530 |
xviexpsp: VSX Vector Insert Exponent Single Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target/ppc/translate/vsx-impl.inc.c | 26 ++++++++++++++++++++++++++
target/ppc/translate/vsx-ops.inc.c | 2 ++
2 files changed, 28 insertions(+)
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index ed392aa..c86f1b5 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1344,6 +1344,32 @@ static void gen_xsxsigqp(DisasContext *ctx)
}
#endif
+static void gen_xviexpsp(DisasContext *ctx)
+{
+ TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
+ TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
+ TCGv_i64 xah = cpu_vsrh(xA(ctx->opcode));
+ TCGv_i64 xal = cpu_vsrl(xA(ctx->opcode));
+ TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode));
+ TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode));
+ TCGv_i64 t0;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ t0 = tcg_temp_new_i64();
+ tcg_gen_andi_i64(xth, xah, 0x807FFFFF807FFFFF);
+ tcg_gen_andi_i64(t0, xbh, 0xFF000000FF);
+ tcg_gen_shli_i64(t0, t0, 23);
+ tcg_gen_or_i64(xth, xth, t0);
+ tcg_gen_andi_i64(xtl, xal, 0x807FFFFF807FFFFF);
+ tcg_gen_andi_i64(t0, xbl, 0xFF000000FF);
+ tcg_gen_shli_i64(t0, t0, 23);
+ tcg_gen_or_i64(xtl, xtl, t0);
+ tcg_temp_free_i64(t0);
+}
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
diff --git a/target/ppc/translate/vsx-ops.inc.c
b/target/ppc/translate/vsx-ops.inc.c
index 09b91c3..93752f0 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -124,6 +124,8 @@ GEN_HANDLER_E(xsiexpdp, 0x3C, 0x16, 0x1C, 0, PPC_NONE,
PPC2_ISA300),
GEN_VSX_XFORM_300(xsiexpqp, 0x4, 0x1B, 0x00000001),
#endif
+GEN_XX3FORM(xviexpsp, 0x00, 0x1B, PPC2_ISA300),
+
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
--
2.7.4
- [Qemu-ppc] [PATCH 00/11] POWER9 TCG enablements - part11, Nikunj A Dadhania, 2017/01/10
- [Qemu-ppc] [PATCH 04/11] target-ppc: Add xsiexpqp instruction, Nikunj A Dadhania, 2017/01/10
- [Qemu-ppc] [PATCH 06/11] target-ppc: Add xviexpdp instruction, Nikunj A Dadhania, 2017/01/10
- [Qemu-ppc] [PATCH 05/11] target-ppc: Add xviexpsp instruction,
Nikunj A Dadhania <=
- [Qemu-ppc] [PATCH 07/11] target-ppc: Add xvxexpsp instruction, Nikunj A Dadhania, 2017/01/10
- [Qemu-ppc] [PATCH 09/11] target-ppc: Add xvxsigsp instruction, Nikunj A Dadhania, 2017/01/10
- [Qemu-ppc] [PATCH 08/11] target-ppc: Add xvxexpdp instruction, Nikunj A Dadhania, 2017/01/10
- [Qemu-ppc] [PATCH 10/11] target-ppc: Add xvxsigdp instruction, Nikunj A Dadhania, 2017/01/10
- [Qemu-ppc] [PATCH 11/11] target-ppc: Add xscvqps[d, w]z instructions, Nikunj A Dadhania, 2017/01/10
- Re: [Qemu-ppc] [PATCH 00/11] POWER9 TCG enablements - part11, David Gibson, 2017/01/11
- Re: [Qemu-ppc] [PATCH 00/11] POWER9 TCG enablements - part11, David Gibson, 2017/01/12