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Re: [Qemu-ppc] [PATCH 03/11] target-ppc: Add xsiexpdp instruction
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH 03/11] target-ppc: Add xsiexpdp instruction |
Date: |
Thu, 12 Jan 2017 13:47:43 +1100 |
User-agent: |
Mutt/1.7.1 (2016-10-04) |
On Tue, Jan 10, 2017 at 02:20:35PM +0530, Nikunj A Dadhania wrote:
> xsiexpdp: VSX Scalar Insert Exponent Double Precision
>
> Signed-off-by: Nikunj A Dadhania <address@hidden>
> ---
> target/ppc/translate/vsx-impl.inc.c | 20 ++++++++++++++++++++
> target/ppc/translate/vsx-ops.inc.c | 1 +
> 2 files changed, 21 insertions(+)
>
> diff --git a/target/ppc/translate/vsx-impl.inc.c
> b/target/ppc/translate/vsx-impl.inc.c
> index 2d9fe50..2d09225 100644
> --- a/target/ppc/translate/vsx-impl.inc.c
> +++ b/target/ppc/translate/vsx-impl.inc.c
> @@ -1243,6 +1243,26 @@ static void gen_xsxexpqp(DisasContext *ctx)
> tcg_gen_movi_i64(xtl, 0);
> }
>
> +static void gen_xsiexpdp(DisasContext *ctx)
> +{
> + TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
> + TCGv ra = cpu_gpr[rA(ctx->opcode)];
> + TCGv rb = cpu_gpr[rB(ctx->opcode)];
> + TCGv_i64 t0;
> +
> + if (unlikely(!ctx->vsx_enabled)) {
> + gen_exception(ctx, POWERPC_EXCP_VSXU);
> + return;
> + }
> + t0 = tcg_temp_new_i64();
> + tcg_gen_andi_i64(xth, ra, 0x800FFFFFFFFFFFFF);
> + tcg_gen_andi_i64(t0, rb, 0x7FF);
> + tcg_gen_shli_i64(t0, t0, 52);
> + tcg_gen_or_i64(xth, xth, t0);
> + /* dword[1] is undefined */
According to the ISA doc I have, dword[1] is set to 0 rather than
being undefined.
> + tcg_temp_free_i64(t0);
> +}
> +
> static void gen_xsxsigdp(DisasContext *ctx)
> {
> TCGv rt = cpu_gpr[rD(ctx->opcode)];
> diff --git a/target/ppc/translate/vsx-ops.inc.c
> b/target/ppc/translate/vsx-ops.inc.c
> index aeeaff2..5980ac6 100644
> --- a/target/ppc/translate/vsx-ops.inc.c
> +++ b/target/ppc/translate/vsx-ops.inc.c
> @@ -120,6 +120,7 @@ GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),
> GEN_VSX_XFORM_300_EO(xsxexpqp, 0x04, 0x19, 0x02, 0x00000001),
> GEN_XX2FORM_EO(xsxsigdp, 0x16, 0x15, 0x01, PPC2_ISA300),
> GEN_VSX_XFORM_300_EO(xsxsigqp, 0x04, 0x19, 0x12, 0x00000001),
> +GEN_HANDLER_E(xsiexpdp, 0x3C, 0x16, 0x1C, 0, PPC_NONE, PPC2_ISA300),
> #endif
>
> GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-ppc] [PATCH 00/11] POWER9 TCG enablements - part11, Nikunj A Dadhania, 2017/01/10
- [Qemu-ppc] [PATCH 04/11] target-ppc: Add xsiexpqp instruction, Nikunj A Dadhania, 2017/01/10
- [Qemu-ppc] [PATCH 06/11] target-ppc: Add xviexpdp instruction, Nikunj A Dadhania, 2017/01/10
- [Qemu-ppc] [PATCH 05/11] target-ppc: Add xviexpsp instruction, Nikunj A Dadhania, 2017/01/10
- [Qemu-ppc] [PATCH 07/11] target-ppc: Add xvxexpsp instruction, Nikunj A Dadhania, 2017/01/10
- [Qemu-ppc] [PATCH 09/11] target-ppc: Add xvxsigsp instruction, Nikunj A Dadhania, 2017/01/10
- [Qemu-ppc] [PATCH 08/11] target-ppc: Add xvxexpdp instruction, Nikunj A Dadhania, 2017/01/10
- [Qemu-ppc] [PATCH 10/11] target-ppc: Add xvxsigdp instruction, Nikunj A Dadhania, 2017/01/10
- [Qemu-ppc] [PATCH 11/11] target-ppc: Add xscvqps[d, w]z instructions, Nikunj A Dadhania, 2017/01/10