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[Qemu-ppc] [PATCH 01/11] target-ppc: xscvqpdp zero VSR
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [PATCH 01/11] target-ppc: xscvqpdp zero VSR |
Date: |
Tue, 10 Jan 2017 14:20:33 +0530 |
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target/ppc/fpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 8c8e3c5..77f68e9 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2787,7 +2787,7 @@ void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode)
ppc_vsr_t xt, xb;
getVSR(rB(opcode) + 32, &xb, env);
- getVSR(rD(opcode) + 32, &xt, env);
+ memset(&xt, 0, sizeof(xt));
if (unlikely(Rc(opcode) != 0)) {
/* TODO: Support xscvqpdpo after round-to-odd is implemented */
--
2.7.4
- [Qemu-ppc] [PATCH 00/11] POWER9 TCG enablements - part11, Nikunj A Dadhania, 2017/01/10
- [Qemu-ppc] [PATCH 04/11] target-ppc: Add xsiexpqp instruction, Nikunj A Dadhania, 2017/01/10
- [Qemu-ppc] [PATCH 06/11] target-ppc: Add xviexpdp instruction, Nikunj A Dadhania, 2017/01/10
- [Qemu-ppc] [PATCH 05/11] target-ppc: Add xviexpsp instruction, Nikunj A Dadhania, 2017/01/10
- [Qemu-ppc] [PATCH 07/11] target-ppc: Add xvxexpsp instruction, Nikunj A Dadhania, 2017/01/10
- [Qemu-ppc] [PATCH 09/11] target-ppc: Add xvxsigsp instruction, Nikunj A Dadhania, 2017/01/10