Re: [PATCH v3 07/19] target/riscv: Refactor some of the generic vector f

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Re: [PATCH v3 07/19] target/riscv: Refactor some of the generic vector f

From:	Weiwei Li
Subject:	Re: [PATCH v3 07/19] target/riscv: Refactor some of the generic vector functionality
Date:	Sat, 29 Apr 2023 11:10:50 +0800
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0


On 2023/4/28 22:47, Lawrence Hunter wrote:

From: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>

Move some macros out of `vector_helper` and into `vector_internals`.
This ensures they can be used by both vector and vector-crypto helpers
(latter implemented in proceeding commits).

Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
---


Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Weiwei Li

  target/riscv/vector_helper.c    | 42 ------------------------------
  target/riscv/vector_internals.h | 46 +++++++++++++++++++++++++++++++++
  2 files changed, 46 insertions(+), 42 deletions(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 27fefef10ec..a438f5d95e1 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -646,9 +646,6 @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b)
  #define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t
  #define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t
  #define OP_SUS_D int64_t, uint64_t, int64_t, uint64_t, int64_t
-#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t
-#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t
-#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t
  #define WOP_SSS_B int16_t, int8_t, int8_t, int16_t, int16_t
  #define WOP_SSS_H int32_t, int16_t, int16_t, int32_t, int32_t
  #define WOP_SSS_W int64_t, int32_t, int32_t, int64_t, int64_t
@@ -3412,11 +3409,6 @@ GEN_VEXT_VF(vfwnmsac_vf_h, 4)
  GEN_VEXT_VF(vfwnmsac_vf_w, 8)

/* Vector Floating-Point Square-Root Instruction */

-/* (TD, T2, TX2) */
-#define OP_UU_H uint16_t, uint16_t, uint16_t
-#define OP_UU_W uint32_t, uint32_t, uint32_t
-#define OP_UU_D uint64_t, uint64_t, uint64_t
-
  #define OPFVV1(NAME, TD, T2, TX2, HD, HS2, OP)        \
  static void do_##NAME(void *vd, void *vs2, int i,      \
          CPURISCVState *env)                            \
@@ -4109,40 +4101,6 @@ GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32)
  GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64)

/* Vector Floating-Point Classify Instruction */

-#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP)         \
-static void do_##NAME(void *vd, void *vs2, int i)      \
-{                                                      \
-    TX2 s2 = *((T2 *)vs2 + HS2(i));                    \
-    *((TD *)vd + HD(i)) = OP(s2);                      \
-}
-
-#define GEN_VEXT_V(NAME, ESZ)                          \
-void HELPER(NAME)(void *vd, void *v0, void *vs2,       \
-                  CPURISCVState *env, uint32_t desc)   \
-{                                                      \
-    uint32_t vm = vext_vm(desc);                       \
-    uint32_t vl = env->vl;                             \
-    uint32_t total_elems =                             \
-        vext_get_total_elems(env, desc, ESZ);          \
-    uint32_t vta = vext_vta(desc);                     \
-    uint32_t vma = vext_vma(desc);                     \
-    uint32_t i;                                        \
-                                                       \
-    for (i = env->vstart; i < vl; i++) {               \
-        if (!vm && !vext_elem_mask(v0, i)) {           \
-            /* set masked-off elements to 1s */        \
-            vext_set_elems_1s(vd, vma, i * ESZ,        \
-                              (i + 1) * ESZ);          \
-            continue;                                  \
-        }                                              \
-        do_##NAME(vd, vs2, i);                         \
-    }                                                  \
-    env->vstart = 0;                                   \
-    /* set tail elements to 1s */                      \
-    vext_set_elems_1s(vd, vta, vl * ESZ,               \
-                      total_elems * ESZ);              \
-}
-
  target_ulong fclass_h(uint64_t frs1)
  {
      float16 f = frs1;
diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h
index 749d138bebe..8133111e5f6 100644
--- a/target/riscv/vector_internals.h
+++ b/target/riscv/vector_internals.h
@@ -121,12 +121,52 @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, 
uint32_t cnt,
  /* expand macro args before macro */
  #define RVVCALL(macro, ...)  macro(__VA_ARGS__)

+/* (TD, T2, TX2) */

+#define OP_UU_B uint8_t, uint8_t, uint8_t
+#define OP_UU_H uint16_t, uint16_t, uint16_t
+#define OP_UU_W uint32_t, uint32_t, uint32_t
+#define OP_UU_D uint64_t, uint64_t, uint64_t
+
  /* (TD, T1, T2, TX1, TX2) */
  #define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t
  #define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t
  #define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t
  #define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t

+#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \

+static void do_##NAME(void *vd, void *vs2, int i)      \
+{                                                      \
+    TX2 s2 = *((T2 *)vs2 + HS2(i));                    \
+    *((TD *)vd + HD(i)) = OP(s2);                      \
+}
+
+#define GEN_VEXT_V(NAME, ESZ)                          \
+void HELPER(NAME)(void *vd, void *v0, void *vs2,       \
+                  CPURISCVState *env, uint32_t desc)   \
+{                                                      \
+    uint32_t vm = vext_vm(desc);                       \
+    uint32_t vl = env->vl;                             \
+    uint32_t total_elems =                             \
+        vext_get_total_elems(env, desc, ESZ);          \
+    uint32_t vta = vext_vta(desc);                     \
+    uint32_t vma = vext_vma(desc);                     \
+    uint32_t i;                                        \
+                                                       \
+    for (i = env->vstart; i < vl; i++) {               \
+        if (!vm && !vext_elem_mask(v0, i)) {           \
+            /* set masked-off elements to 1s */        \
+            vext_set_elems_1s(vd, vma, i * ESZ,        \
+                              (i + 1) * ESZ);          \
+            continue;                                  \
+        }                                              \
+        do_##NAME(vd, vs2, i);                         \
+    }                                                  \
+    env->vstart = 0;                                   \
+    /* set tail elements to 1s */                      \
+    vext_set_elems_1s(vd, vta, vl * ESZ,               \
+                      total_elems * ESZ);              \
+}
+
  /* operation of two vector elements */
  typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);

@@ -179,4 +219,10 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \

                 do_##NAME, ESZ);                           \
  }

+/* Three of the widening shortening macros: */

+/* (TD, T1, T2, TX1, TX2) */
+#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t
+#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t
+#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t
+
  #endif /* TARGET_RISCV_VECTOR_INTERNALS_H */

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Re: [PATCH v3 05/19] target/riscv: Move vector translation checks, (continued)
- [PATCH v3 03/19] target/riscv: Remove redundant "cpu_vl == 0" checks, Lawrence Hunter, 2023/04/28
  - Re: [PATCH v3 03/19] target/riscv: Remove redundant "cpu_vl == 0" checks, Weiwei Li, 2023/04/28
- [PATCH v3 02/19] target/riscv: Refactor vector-vector translation macro, Lawrence Hunter, 2023/04/28
  - Re: [PATCH v3 02/19] target/riscv: Refactor vector-vector translation macro, Weiwei Li, 2023/04/28
- [PATCH v3 01/19] target/riscv: Refactor some of the generic vector functionality, Lawrence Hunter, 2023/04/28
  - Re: [PATCH v3 01/19] target/riscv: Refactor some of the generic vector functionality, Weiwei Li, 2023/04/28
- [PATCH v3 04/19] target/riscv: Add Zvbc ISA extension support, Lawrence Hunter, 2023/04/28
  - Re: [PATCH v3 04/19] target/riscv: Add Zvbc ISA extension support, Weiwei Li, 2023/04/28
- [PATCH v3 07/19] target/riscv: Refactor some of the generic vector functionality, Lawrence Hunter, 2023/04/28
  - Re: [PATCH v3 07/19] target/riscv: Refactor some of the generic vector functionality, Weiwei Li <=
- [PATCH v3 09/19] tcg: Add andcs and rotrs tcg gvec ops, Lawrence Hunter, 2023/04/28
- [PATCH v3 08/19] qemu/bitops.h: Limit rotate amounts, Lawrence Hunter, 2023/04/28
- [PATCH v3 10/19] qemu/host-utils.h: Add clz and ctz functions for lower-bit integers, Lawrence Hunter, 2023/04/28
- [PATCH v3 13/19] target/riscv: Add Zvknh ISA extension support, Lawrence Hunter, 2023/04/28
- [PATCH v3 14/19] target/riscv: Add Zvksh ISA extension support, Lawrence Hunter, 2023/04/28
- [PATCH v3 19/19] target/riscv: Expose Zvk* and Zvb[b, c] cpu properties, Lawrence Hunter, 2023/04/28
  - Re: [PATCH v3 19/19] target/riscv: Expose Zvk* and Zvb[b, c] cpu properties, Weiwei Li, 2023/04/28
- [PATCH v3 11/19] target/riscv: Add Zvbb ISA extension support, Lawrence Hunter, 2023/04/28
  - Re: [PATCH v3 11/19] target/riscv: Add Zvbb ISA extension support, Weiwei Li, 2023/04/28
- [PATCH v3 17/19] crypto: Add SM4 constant parameter CK, Lawrence Hunter, 2023/04/28

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