Re: [PATCH v3 03/19] target/riscv: Remove redundant "cpu

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Re: [PATCH v3 03/19] target/riscv: Remove redundant "cpu_vl == 0" checks

From:	Weiwei Li
Subject:	Re: [PATCH v3 03/19] target/riscv: Remove redundant "cpu_vl == 0" checks
Date:	Sat, 29 Apr 2023 10:36:27 +0800
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0


On 2023/4/28 22:47, Lawrence Hunter wrote:

From: Nazar Kazakov <nazar.kazakov@codethink.co.uk>

Remove the redundant "vl == 0" check which is already included within the  vstart 
>= vl check, when vl == 0.

Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
---

Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Weiwei Li

  target/riscv/insn_trans/trans_rvv.c.inc | 31 +------------------------
  1 file changed, 1 insertion(+), 30 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index 4106bd69949..2660dda42be 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -617,7 +617,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, 
uint32_t data,
      TCGv_i32 desc;

TCGLabel *over = gen_new_label();

-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
      tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

dest = tcg_temp_new_ptr();

@@ -786,7 +785,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, 
uint32_t rs2,
      TCGv_i32 desc;

TCGLabel *over = gen_new_label();

-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
      tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

dest = tcg_temp_new_ptr();

@@ -893,7 +891,6 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, 
uint32_t vs2,
      TCGv_i32 desc;

TCGLabel *over = gen_new_label();

-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
      tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

dest = tcg_temp_new_ptr();

@@ -1034,7 +1031,6 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, 
uint32_t data,
      TCGv_i32 desc;

TCGLabel *over = gen_new_label();

-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
      tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

dest = tcg_temp_new_ptr();

@@ -1191,7 +1187,6 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn 
*gvec_fn,
          return false;
      }

- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);

      tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {

@@ -1241,7 +1236,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, 
uint32_t vs2, uint32_t vm,
      uint32_t data = 0;

TCGLabel *over = gen_new_label();

-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
      tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

dest = tcg_temp_new_ptr();

@@ -1405,7 +1399,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, 
uint32_t vs2, uint32_t vm,
      uint32_t data = 0;

TCGLabel *over = gen_new_label();

-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
      tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

dest = tcg_temp_new_ptr();

@@ -1492,7 +1485,6 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
      if (checkfn(s, a)) {
          uint32_t data = 0;
          TCGLabel *over = gen_new_label();
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

data = FIELD_DP32(data, VDATA, VM, a->vm);

@@ -1575,7 +1567,6 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
      if (opiwv_widen_check(s, a)) {
          uint32_t data = 0;
          TCGLabel *over = gen_new_label();
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

data = FIELD_DP32(data, VDATA, VM, a->vm);

@@ -1648,7 +1639,6 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, 
uint32_t vs2, uint32_t vm,
  {
      uint32_t data = 0;
      TCGLabel *over = gen_new_label();
-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
      tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

data = FIELD_DP32(data, VDATA, VM, vm);

@@ -1842,7 +1832,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)    
         \
              gen_helper_##NAME##_w,                                 \
          };                                                         \
          TCGLabel *over = gen_new_label();                          \
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
@@ -2054,7 +2043,6 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
                  gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
              };
              TCGLabel *over = gen_new_label();
-            tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
              tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),

@@ -2078,7 +2066,6 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
          vext_check_ss(s, a->rd, 0, 1)) {
          TCGv s1;
          TCGLabel *over = gen_new_label();
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

s1 = get_gpr(s, a->rs1, EXT_SIGN);

@@ -2140,7 +2127,6 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
                  gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
              };
              TCGLabel *over = gen_new_label();
-            tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
              tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

s1 = tcg_constant_i64(simm);

@@ -2288,7 +2274,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)    
         \
          };                                                         \
          TCGLabel *over = gen_new_label();                          \
          gen_set_rm(s, RISCV_FRM_DYN);                              \
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
@@ -2323,7 +2308,6 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, 
uint32_t vs2,
      TCGv_i64 t1;

TCGLabel *over = gen_new_label();

-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
      tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

dest = tcg_temp_new_ptr();

@@ -2408,7 +2392,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)    
       \
          };                                                       \
          TCGLabel *over = gen_new_label();                        \
          gen_set_rm(s, RISCV_FRM_DYN);                            \
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);        \
          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);\
                                                                   \
          data = FIELD_DP32(data, VDATA, VM, a->vm);               \
@@ -2483,7 +2466,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)    
         \
          };                                                         \
          TCGLabel *over = gen_new_label();                          \
          gen_set_rm(s, RISCV_FRM_DYN);                              \
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
@@ -2601,7 +2583,6 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
          uint32_t data = 0;
          TCGLabel *over = gen_new_label();
          gen_set_rm_chkfrm(s, rm);
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

data = FIELD_DP32(data, VDATA, VM, a->vm);

@@ -2713,7 +2694,6 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f 
*a)
                  gen_helper_vmv_v_x_d,
              };
              TCGLabel *over = gen_new_label();
-            tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
              tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

t1 = tcg_temp_new_i64();

@@ -2792,7 +2772,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)     
         \
          };                                                         \
          TCGLabel *over = gen_new_label();                          \
          gen_set_rm_chkfrm(s, FRM);                                 \
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
@@ -2844,7 +2823,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)     
         \
          };                                                         \
          TCGLabel *over = gen_new_label();                          \
          gen_set_rm(s, RISCV_FRM_DYN);                              \
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
@@ -2912,7 +2890,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)     
         \
          };                                                         \
          TCGLabel *over = gen_new_label();                          \
          gen_set_rm_chkfrm(s, FRM);                                 \
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
@@ -2962,7 +2939,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)     
         \
          };                                                         \
          TCGLabel *over = gen_new_label();                          \
          gen_set_rm_chkfrm(s, FRM);                                 \
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
          data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
@@ -3053,7 +3029,6 @@ static bool trans_##NAME(DisasContext *s, arg_r *a)       
         \
          uint32_t data = 0;                                         \
          gen_helper_gvec_4_ptr *fn = gen_helper_##NAME;             \
          TCGLabel *over = gen_new_label();                          \
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
          data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
@@ -3222,7 +3197,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
          require_vm(a->vm, a->rd)) {
          uint32_t data = 0;
          TCGLabel *over = gen_new_label();
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

data = FIELD_DP32(data, VDATA, VM, a->vm);

@@ -3409,7 +3383,6 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
          TCGv s1;
          TCGLabel *over = gen_new_label();

- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);

          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

t1 = tcg_temp_new_i64();

@@ -3466,8 +3439,7 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f 
*a)
          TCGv_i64 t1;
          TCGLabel *over = gen_new_label();

- /* if vl == 0 or vstart >= vl, skip vector register write back */

-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+        /* if vstart >= vl, skip vector register write back */
          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

/* NaN-box f[rs1] */

@@ -3718,7 +3690,6 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, 
uint8_t seq)
      uint32_t data = 0;
      gen_helper_gvec_3_ptr *fn;
      TCGLabel *over = gen_new_label();
-    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
      tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

static gen_helper_gvec_3_ptr * const fns[6][4] = {

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[PATCH v3 00/19] Add RISC-V vector cryptographic instruction set support, Lawrence Hunter, 2023/04/28
- [PATCH v3 06/19] target/riscv: Refactor translation of vector-widening instruction, Lawrence Hunter, 2023/04/28
  - Re: [PATCH v3 06/19] target/riscv: Refactor translation of vector-widening instruction, Weiwei Li, 2023/04/28
- [PATCH v3 05/19] target/riscv: Move vector translation checks, Lawrence Hunter, 2023/04/28
  - Re: [PATCH v3 05/19] target/riscv: Move vector translation checks, Weiwei Li, 2023/04/28
- [PATCH v3 03/19] target/riscv: Remove redundant "cpu_vl == 0" checks, Lawrence Hunter, 2023/04/28
  - Re: [PATCH v3 03/19] target/riscv: Remove redundant "cpu_vl == 0" checks, Weiwei Li <=
- [PATCH v3 02/19] target/riscv: Refactor vector-vector translation macro, Lawrence Hunter, 2023/04/28
  - Re: [PATCH v3 02/19] target/riscv: Refactor vector-vector translation macro, Weiwei Li, 2023/04/28
- [PATCH v3 01/19] target/riscv: Refactor some of the generic vector functionality, Lawrence Hunter, 2023/04/28
  - Re: [PATCH v3 01/19] target/riscv: Refactor some of the generic vector functionality, Weiwei Li, 2023/04/28
- [PATCH v3 04/19] target/riscv: Add Zvbc ISA extension support, Lawrence Hunter, 2023/04/28
  - Re: [PATCH v3 04/19] target/riscv: Add Zvbc ISA extension support, Weiwei Li, 2023/04/28
- [PATCH v3 07/19] target/riscv: Refactor some of the generic vector functionality, Lawrence Hunter, 2023/04/28
  - Re: [PATCH v3 07/19] target/riscv: Refactor some of the generic vector functionality, Weiwei Li, 2023/04/28
- [PATCH v3 09/19] tcg: Add andcs and rotrs tcg gvec ops, Lawrence Hunter, 2023/04/28
- [PATCH v3 08/19] qemu/bitops.h: Limit rotate amounts, Lawrence Hunter, 2023/04/28

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