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[PATCH v3 08/19] qemu/bitops.h: Limit rotate amounts
From: |
Lawrence Hunter |
Subject: |
[PATCH v3 08/19] qemu/bitops.h: Limit rotate amounts |
Date: |
Fri, 28 Apr 2023 15:47:46 +0100 |
From: Dickon Hood <dickon.hood@codethink.co.uk>
Rotates have been fixed up to only allow for reasonable rotate amounts
(ie, no rotates >7 on an 8b value etc.) This fixes a problem with riscv
vector rotate instructions.
Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/qemu/bitops.h | 24 ++++++++++++++++--------
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index 03213ce952c..c443995b3ba 100644
--- a/include/qemu/bitops.h
+++ b/include/qemu/bitops.h
@@ -218,7 +218,8 @@ static inline unsigned long find_first_zero_bit(const
unsigned long *addr,
*/
static inline uint8_t rol8(uint8_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((8 - shift) & 7));
+ shift &= 7;
+ return (word << shift) | (word >> (8 - shift));
}
/**
@@ -228,7 +229,8 @@ static inline uint8_t rol8(uint8_t word, unsigned int shift)
*/
static inline uint8_t ror8(uint8_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((8 - shift) & 7));
+ shift &= 7;
+ return (word >> shift) | (word << (8 - shift));
}
/**
@@ -238,7 +240,8 @@ static inline uint8_t ror8(uint8_t word, unsigned int shift)
*/
static inline uint16_t rol16(uint16_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((16 - shift) & 15));
+ shift &= 15;
+ return (word << shift) | (word >> (16 - shift));
}
/**
@@ -248,7 +251,8 @@ static inline uint16_t rol16(uint16_t word, unsigned int
shift)
*/
static inline uint16_t ror16(uint16_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((16 - shift) & 15));
+ shift &= 15;
+ return (word >> shift) | (word << (16 - shift));
}
/**
@@ -258,7 +262,8 @@ static inline uint16_t ror16(uint16_t word, unsigned int
shift)
*/
static inline uint32_t rol32(uint32_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((32 - shift) & 31));
+ shift &= 31;
+ return (word << shift) | (word >> (32 - shift));
}
/**
@@ -268,7 +273,8 @@ static inline uint32_t rol32(uint32_t word, unsigned int
shift)
*/
static inline uint32_t ror32(uint32_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((32 - shift) & 31));
+ shift &= 31;
+ return (word >> shift) | (word << (32 - shift));
}
/**
@@ -278,7 +284,8 @@ static inline uint32_t ror32(uint32_t word, unsigned int
shift)
*/
static inline uint64_t rol64(uint64_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((64 - shift) & 63));
+ shift &= 63;
+ return (word << shift) | (word >> (64 - shift));
}
/**
@@ -288,7 +295,8 @@ static inline uint64_t rol64(uint64_t word, unsigned int
shift)
*/
static inline uint64_t ror64(uint64_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((64 - shift) & 63));
+ shift &= 63;
+ return (word >> shift) | (word << (64 - shift));
}
/**
--
2.40.1
- Re: [PATCH v3 03/19] target/riscv: Remove redundant "cpu_vl == 0" checks, (continued)
- [PATCH v3 02/19] target/riscv: Refactor vector-vector translation macro, Lawrence Hunter, 2023/04/28
- [PATCH v3 01/19] target/riscv: Refactor some of the generic vector functionality, Lawrence Hunter, 2023/04/28
- [PATCH v3 04/19] target/riscv: Add Zvbc ISA extension support, Lawrence Hunter, 2023/04/28
- [PATCH v3 07/19] target/riscv: Refactor some of the generic vector functionality, Lawrence Hunter, 2023/04/28
- [PATCH v3 09/19] tcg: Add andcs and rotrs tcg gvec ops, Lawrence Hunter, 2023/04/28
- [PATCH v3 08/19] qemu/bitops.h: Limit rotate amounts,
Lawrence Hunter <=
- [PATCH v3 10/19] qemu/host-utils.h: Add clz and ctz functions for lower-bit integers, Lawrence Hunter, 2023/04/28
- [PATCH v3 13/19] target/riscv: Add Zvknh ISA extension support, Lawrence Hunter, 2023/04/28
- [PATCH v3 14/19] target/riscv: Add Zvksh ISA extension support, Lawrence Hunter, 2023/04/28
- [PATCH v3 19/19] target/riscv: Expose Zvk* and Zvb[b, c] cpu properties, Lawrence Hunter, 2023/04/28
- [PATCH v3 11/19] target/riscv: Add Zvbb ISA extension support, Lawrence Hunter, 2023/04/28
- [PATCH v3 17/19] crypto: Add SM4 constant parameter CK, Lawrence Hunter, 2023/04/28
- [PATCH v3 12/19] target/riscv: Add Zvkned ISA extension support, Lawrence Hunter, 2023/04/28
- [PATCH v3 16/19] crypto: Create sm4_subword, Lawrence Hunter, 2023/04/28