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[PATCH v3 10/19] qemu/host-utils.h: Add clz and ctz functions for lower-
From: |
Lawrence Hunter |
Subject: |
[PATCH v3 10/19] qemu/host-utils.h: Add clz and ctz functions for lower-bit integers |
Date: |
Fri, 28 Apr 2023 15:47:48 +0100 |
From: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
This is for use in the RISC-V vclz and vctz instructions (implemented in
proceeding commit).
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/qemu/host-utils.h | 54 +++++++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h
index 3ce62bf4a56..d3b4dce6a93 100644
--- a/include/qemu/host-utils.h
+++ b/include/qemu/host-utils.h
@@ -107,6 +107,36 @@ static inline uint64_t muldiv64(uint64_t a, uint32_t b,
uint32_t c)
}
#endif
+/**
+ * clz8 - count leading zeros in a 8-bit value.
+ * @val: The value to search
+ *
+ * Returns 8 if the value is zero. Note that the GCC builtin is
+ * undefined if the value is zero.
+ *
+ * Note that the GCC builtin will upcast its argument to an `unsigned int`
+ * so this function subtracts off the number of prepended zeroes.
+ */
+static inline int clz8(uint8_t val)
+{
+ return val ? __builtin_clz(val) - 24 : 8;
+}
+
+/**
+ * clz16 - count leading zeros in a 16-bit value.
+ * @val: The value to search
+ *
+ * Returns 16 if the value is zero. Note that the GCC builtin is
+ * undefined if the value is zero.
+ *
+ * Note that the GCC builtin will upcast its argument to an `unsigned int`
+ * so this function subtracts off the number of prepended zeroes.
+ */
+static inline int clz16(uint16_t val)
+{
+ return val ? __builtin_clz(val) - 16 : 16;
+}
+
/**
* clz32 - count leading zeros in a 32-bit value.
* @val: The value to search
@@ -153,6 +183,30 @@ static inline int clo64(uint64_t val)
return clz64(~val);
}
+/**
+ * ctz8 - count trailing zeros in a 8-bit value.
+ * @val: The value to search
+ *
+ * Returns 8 if the value is zero. Note that the GCC builtin is
+ * undefined if the value is zero.
+ */
+static inline int ctz8(uint8_t val)
+{
+ return val ? __builtin_ctz(val) : 8;
+}
+
+/**
+ * ctz16 - count trailing zeros in a 16-bit value.
+ * @val: The value to search
+ *
+ * Returns 16 if the value is zero. Note that the GCC builtin is
+ * undefined if the value is zero.
+ */
+static inline int ctz16(uint16_t val)
+{
+ return val ? __builtin_ctz(val) : 16;
+}
+
/**
* ctz32 - count trailing zeros in a 32-bit value.
* @val: The value to search
--
2.40.1
- [PATCH v3 02/19] target/riscv: Refactor vector-vector translation macro, (continued)
- [PATCH v3 02/19] target/riscv: Refactor vector-vector translation macro, Lawrence Hunter, 2023/04/28
- [PATCH v3 01/19] target/riscv: Refactor some of the generic vector functionality, Lawrence Hunter, 2023/04/28
- [PATCH v3 04/19] target/riscv: Add Zvbc ISA extension support, Lawrence Hunter, 2023/04/28
- [PATCH v3 07/19] target/riscv: Refactor some of the generic vector functionality, Lawrence Hunter, 2023/04/28
- [PATCH v3 09/19] tcg: Add andcs and rotrs tcg gvec ops, Lawrence Hunter, 2023/04/28
- [PATCH v3 08/19] qemu/bitops.h: Limit rotate amounts, Lawrence Hunter, 2023/04/28
- [PATCH v3 10/19] qemu/host-utils.h: Add clz and ctz functions for lower-bit integers,
Lawrence Hunter <=
- [PATCH v3 13/19] target/riscv: Add Zvknh ISA extension support, Lawrence Hunter, 2023/04/28
- [PATCH v3 14/19] target/riscv: Add Zvksh ISA extension support, Lawrence Hunter, 2023/04/28
- [PATCH v3 19/19] target/riscv: Expose Zvk* and Zvb[b, c] cpu properties, Lawrence Hunter, 2023/04/28
- [PATCH v3 11/19] target/riscv: Add Zvbb ISA extension support, Lawrence Hunter, 2023/04/28
- [PATCH v3 17/19] crypto: Add SM4 constant parameter CK, Lawrence Hunter, 2023/04/28
- [PATCH v3 12/19] target/riscv: Add Zvkned ISA extension support, Lawrence Hunter, 2023/04/28
- [PATCH v3 16/19] crypto: Create sm4_subword, Lawrence Hunter, 2023/04/28
- [PATCH v3 15/19] target/riscv: Add Zvkg ISA extension support, Lawrence Hunter, 2023/04/28