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[PATCH v5 13/13] target/riscv: Deny access if access is partially inside
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From: |
Weiwei Li |
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Subject: |
[PATCH v5 13/13] target/riscv: Deny access if access is partially inside the PMP entry |
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Date: |
Fri, 28 Apr 2023 22:36:21 +0800 |
Access will fails if access is partially inside the PMP entry.
However,only set ret = false doesn't really mean pmp violation
since pmp_hart_has_privs_default() may return true at the end of
pmp_hart_has_privs().
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/pmp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 317c28ba73..1ee8899d04 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -327,8 +327,8 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong
addr,
if ((s + e) == 1) {
qemu_log_mask(LOG_GUEST_ERROR,
"pmp violation - access is partially inside\n");
- ret = false;
- break;
+ *allowed_privs = 0;
+ return false;
}
/* fully inside */
--
2.25.1
- [PATCH v5 00/13] target/riscv: Fix PMP related problem, Weiwei Li, 2023/04/28
- [PATCH v5 02/13] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp, Weiwei Li, 2023/04/28
- [PATCH v5 07/13] target/riscv: Flush TLB when MMWP or MML bits are changed, Weiwei Li, 2023/04/28
- [PATCH v5 04/13] target/riscv: Change the return type of pmp_hart_has_privs() to bool, Weiwei Li, 2023/04/28
- [PATCH v5 03/13] target/riscv: Make the short cut really work in pmp_hart_has_privs, Weiwei Li, 2023/04/28
- [PATCH v5 06/13] target/riscv: Remove unused paramters in pmp_hart_has_privs_default(), Weiwei Li, 2023/04/28
- [PATCH v5 05/13] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled, Weiwei Li, 2023/04/28
- [PATCH v5 01/13] target/riscv: Update pmp_get_tlb_size(), Weiwei Li, 2023/04/28
- [PATCH v5 10/13] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes, Weiwei Li, 2023/04/28
- [PATCH v5 08/13] target/riscv: Update the next rule addr in pmpaddr_csr_write(), Weiwei Li, 2023/04/28
- [PATCH v5 13/13] target/riscv: Deny access if access is partially inside the PMP entry,
Weiwei Li <=
- [PATCH v5 12/13] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write, Weiwei Li, 2023/04/28
- [PATCH v5 11/13] accel/tcg: Uncache the host address for instruction fetch when tlb size < 1, Weiwei Li, 2023/04/28
- [PATCH v5 09/13] target/riscv: Flush TLB when pmpaddr is updated, Weiwei Li, 2023/04/28