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[PATCH v5 07/13] target/riscv: Flush TLB when MMWP or MML bits are chang
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From: |
Weiwei Li |
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Subject: |
[PATCH v5 07/13] target/riscv: Flush TLB when MMWP or MML bits are changed |
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Date: |
Fri, 28 Apr 2023 22:36:15 +0800 |
MMWP and MML bits may affect the allowed privs of PMP entries and the
default privs, both of which may change the allowed privs of exsited
TLB entries. So we need flush TLB when they are changed.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/pmp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index d2d8429277..80889a1185 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -578,6 +578,9 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
if (riscv_cpu_cfg(env)->epmp) {
/* Sticky bits */
val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
+ if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) {
+ tlb_flush(env_cpu(env));
+ }
} else {
val &= ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB);
}
--
2.25.1
- [PATCH v5 00/13] target/riscv: Fix PMP related problem, Weiwei Li, 2023/04/28
- [PATCH v5 02/13] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp, Weiwei Li, 2023/04/28
- [PATCH v5 07/13] target/riscv: Flush TLB when MMWP or MML bits are changed,
Weiwei Li <=
- [PATCH v5 04/13] target/riscv: Change the return type of pmp_hart_has_privs() to bool, Weiwei Li, 2023/04/28
- [PATCH v5 03/13] target/riscv: Make the short cut really work in pmp_hart_has_privs, Weiwei Li, 2023/04/28
- [PATCH v5 06/13] target/riscv: Remove unused paramters in pmp_hart_has_privs_default(), Weiwei Li, 2023/04/28
- [PATCH v5 05/13] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled, Weiwei Li, 2023/04/28
- [PATCH v5 01/13] target/riscv: Update pmp_get_tlb_size(), Weiwei Li, 2023/04/28
- [PATCH v5 10/13] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes, Weiwei Li, 2023/04/28
- [PATCH v5 08/13] target/riscv: Update the next rule addr in pmpaddr_csr_write(), Weiwei Li, 2023/04/28
- [PATCH v5 13/13] target/riscv: Deny access if access is partially inside the PMP entry, Weiwei Li, 2023/04/28
- [PATCH v5 12/13] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write, Weiwei Li, 2023/04/28
- [PATCH v5 11/13] accel/tcg: Uncache the host address for instruction fetch when tlb size < 1, Weiwei Li, 2023/04/28